A scheduler synthesis methodology for joint SW/HW design exploration of SoC
The introduction of high-performance applications such as multimedia applications into SoCs led the manufacturers to provide embedded SoCs able to offer an important computing power which makes it possible to answer the increasing requirements of future evolutions of these applications. One of the a...
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| Acceso en línea: | http://hdl.handle.net/20.500.12110/paper_09295585_v14_n2_p75_Assayad |
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todo:paper_09295585_v14_n2_p75_Assayad2023-10-03T15:47:35Z A scheduler synthesis methodology for joint SW/HW design exploration of SoC Assayad, I. Yovine, S. Exploration Multiprocessor system-on-chips (SoCs) Real-time requirements Scheduling SW/HW design Component-based models Computing power Exploration High performance applications MPEG-4 video encoders Multi-processor hardware Multimedia applications Multiprocessor system on chips Parallel software Real time requirement SW/HW design Synthesis methodology Synthesis techniques System models Design Motion Picture Experts Group standards Scheduling Timing jitter Multiprocessing systems The introduction of high-performance applications such as multimedia applications into SoCs led the manufacturers to provide embedded SoCs able to offer an important computing power which makes it possible to answer the increasing requirements of future evolutions of these applications. One of the adopted solutions is the use of multiprocessor SoCs. In this paper, we present a joint SW/HW design exploration methodology for multiprocessor SoCs. The system model relies on transaction-level component-based models for modeling parallel software and multiprocessor hardware. Our proposal comprises two original points. First, we propose a composable software-level scheduler constraints synthesis technique. Second, we present a combined software-level and exploratory hardwarelevel schedulers. The methodology has the advantage of combining real-time requirements of software with effective exploitation of multiprocessor hardware. We describe and apply the methodology to synthesize a scheduler of a slice-based MPEG-4 video encoder on the multiprocessor Cake SoCs. © Springer Science+Business Media, LLC 2010. JOUR info:eu-repo/semantics/openAccess http://creativecommons.org/licenses/by/2.5/ar http://hdl.handle.net/20.500.12110/paper_09295585_v14_n2_p75_Assayad |
| institution |
Universidad de Buenos Aires |
| institution_str |
I-28 |
| repository_str |
R-134 |
| collection |
Biblioteca Digital - Facultad de Ciencias Exactas y Naturales (UBA) |
| topic |
Exploration Multiprocessor system-on-chips (SoCs) Real-time requirements Scheduling SW/HW design Component-based models Computing power Exploration High performance applications MPEG-4 video encoders Multi-processor hardware Multimedia applications Multiprocessor system on chips Parallel software Real time requirement SW/HW design Synthesis methodology Synthesis techniques System models Design Motion Picture Experts Group standards Scheduling Timing jitter Multiprocessing systems |
| spellingShingle |
Exploration Multiprocessor system-on-chips (SoCs) Real-time requirements Scheduling SW/HW design Component-based models Computing power Exploration High performance applications MPEG-4 video encoders Multi-processor hardware Multimedia applications Multiprocessor system on chips Parallel software Real time requirement SW/HW design Synthesis methodology Synthesis techniques System models Design Motion Picture Experts Group standards Scheduling Timing jitter Multiprocessing systems Assayad, I. Yovine, S. A scheduler synthesis methodology for joint SW/HW design exploration of SoC |
| topic_facet |
Exploration Multiprocessor system-on-chips (SoCs) Real-time requirements Scheduling SW/HW design Component-based models Computing power Exploration High performance applications MPEG-4 video encoders Multi-processor hardware Multimedia applications Multiprocessor system on chips Parallel software Real time requirement SW/HW design Synthesis methodology Synthesis techniques System models Design Motion Picture Experts Group standards Scheduling Timing jitter Multiprocessing systems |
| description |
The introduction of high-performance applications such as multimedia applications into SoCs led the manufacturers to provide embedded SoCs able to offer an important computing power which makes it possible to answer the increasing requirements of future evolutions of these applications. One of the adopted solutions is the use of multiprocessor SoCs. In this paper, we present a joint SW/HW design exploration methodology for multiprocessor SoCs. The system model relies on transaction-level component-based models for modeling parallel software and multiprocessor hardware. Our proposal comprises two original points. First, we propose a composable software-level scheduler constraints synthesis technique. Second, we present a combined software-level and exploratory hardwarelevel schedulers. The methodology has the advantage of combining real-time requirements of software with effective exploitation of multiprocessor hardware. We describe and apply the methodology to synthesize a scheduler of a slice-based MPEG-4 video encoder on the multiprocessor Cake SoCs. © Springer Science+Business Media, LLC 2010. |
| format |
JOUR |
| author |
Assayad, I. Yovine, S. |
| author_facet |
Assayad, I. Yovine, S. |
| author_sort |
Assayad, I. |
| title |
A scheduler synthesis methodology for joint SW/HW design exploration of SoC |
| title_short |
A scheduler synthesis methodology for joint SW/HW design exploration of SoC |
| title_full |
A scheduler synthesis methodology for joint SW/HW design exploration of SoC |
| title_fullStr |
A scheduler synthesis methodology for joint SW/HW design exploration of SoC |
| title_full_unstemmed |
A scheduler synthesis methodology for joint SW/HW design exploration of SoC |
| title_sort |
scheduler synthesis methodology for joint sw/hw design exploration of soc |
| url |
http://hdl.handle.net/20.500.12110/paper_09295585_v14_n2_p75_Assayad |
| work_keys_str_mv |
AT assayadi aschedulersynthesismethodologyforjointswhwdesignexplorationofsoc AT yovines aschedulersynthesismethodologyforjointswhwdesignexplorationofsoc AT assayadi schedulersynthesismethodologyforjointswhwdesignexplorationofsoc AT yovines schedulersynthesismethodologyforjointswhwdesignexplorationofsoc |
| _version_ |
1807322594296201216 |