Influence of variable time operations in static instruction scheduling

Instruction Scheduling is the task of deciding what instruction will be executed at which unit of time. The objective is to extract maximum instruction level parallelism for the code. Compilers designed for VLIW and EPIC architectures do static instruction scheduling in a back-end pass. This pass, k...

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Detalles Bibliográficos
Autores principales:	Borensztejn, P., Barrado, C., Labarta, J.
Formato:	SER
Materias:	Constant values EPIC architecture Execution time Instruction level parallelism Instruction scheduling Memory hierarchy Software pipelining Variable latencies Scheduling Very long instruction word architecture
Acceso en línea:	http://hdl.handle.net/20.500.12110/paper_03029743_v1685LNCS_n_p213_Borensztejn
Aporte de:	Biblioteca Digital - Facultad de Ciencias Exactas y Naturales (UBA) de Universidad de Buenos Aires

id	todo:paper_03029743_v1685LNCS_n_p213_Borensztejn
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spelling	todo:paper_03029743_v1685LNCS_n_p213_Borensztejn2023-10-03T15:18:51Z Influence of variable time operations in static instruction scheduling Borensztejn, P. Barrado, C. Labarta, J. Constant values EPIC architecture Execution time Instruction level parallelism Instruction scheduling Memory hierarchy Software pipelining Variable latencies Scheduling Very long instruction word architecture Instruction Scheduling is the task of deciding what instruction will be executed at which unit of time. The objective is to extract maximum instruction level parallelism for the code. Compilers designed for VLIW and EPIC architectures do static instruction scheduling in a back-end pass. This pass, known as scheduler, needs to have full knowledge of the execution time of each instruction. But memory access instructions have a variable latency, depending on their locality and the memory hierarchy architecture. The scheduler must assume a constant value, usually the execution time assigned to a hit. At execution a miss may reduce the parallelism because idle cycles may appear before the instructions that need the data. This paper describes a statistic model to evaluate how sensitive are the scheduling algorithms to the variable time operations. We present experimental measures taken over two static scheduling algorithms based on software pipelining. © Springer-Verlag Berlin Heidelberg 1999. SER info:eu-repo/semantics/openAccess http://creativecommons.org/licenses/by/2.5/ar http://hdl.handle.net/20.500.12110/paper_03029743_v1685LNCS_n_p213_Borensztejn
institution	Universidad de Buenos Aires
institution_str	I-28
repository_str	R-134
collection	Biblioteca Digital - Facultad de Ciencias Exactas y Naturales (UBA)
topic	Constant values EPIC architecture Execution time Instruction level parallelism Instruction scheduling Memory hierarchy Software pipelining Variable latencies Scheduling Very long instruction word architecture
spellingShingle	Constant values EPIC architecture Execution time Instruction level parallelism Instruction scheduling Memory hierarchy Software pipelining Variable latencies Scheduling Very long instruction word architecture Borensztejn, P. Barrado, C. Labarta, J. Influence of variable time operations in static instruction scheduling
topic_facet	Constant values EPIC architecture Execution time Instruction level parallelism Instruction scheduling Memory hierarchy Software pipelining Variable latencies Scheduling Very long instruction word architecture
description	Instruction Scheduling is the task of deciding what instruction will be executed at which unit of time. The objective is to extract maximum instruction level parallelism for the code. Compilers designed for VLIW and EPIC architectures do static instruction scheduling in a back-end pass. This pass, known as scheduler, needs to have full knowledge of the execution time of each instruction. But memory access instructions have a variable latency, depending on their locality and the memory hierarchy architecture. The scheduler must assume a constant value, usually the execution time assigned to a hit. At execution a miss may reduce the parallelism because idle cycles may appear before the instructions that need the data. This paper describes a statistic model to evaluate how sensitive are the scheduling algorithms to the variable time operations. We present experimental measures taken over two static scheduling algorithms based on software pipelining. © Springer-Verlag Berlin Heidelberg 1999.
format	SER
author	Borensztejn, P. Barrado, C. Labarta, J.
author_facet	Borensztejn, P. Barrado, C. Labarta, J.
author_sort	Borensztejn, P.
title	Influence of variable time operations in static instruction scheduling
title_short	Influence of variable time operations in static instruction scheduling
title_full	Influence of variable time operations in static instruction scheduling
title_fullStr	Influence of variable time operations in static instruction scheduling
title_full_unstemmed	Influence of variable time operations in static instruction scheduling
title_sort	influence of variable time operations in static instruction scheduling
url	http://hdl.handle.net/20.500.12110/paper_03029743_v1685LNCS_n_p213_Borensztejn
work_keys_str_mv	AT borensztejnp influenceofvariabletimeoperationsinstaticinstructionscheduling AT barradoc influenceofvariabletimeoperationsinstaticinstructionscheduling AT labartaj influenceofvariabletimeoperationsinstaticinstructionscheduling
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Influence of variable time operations in static instruction scheduling

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