Using the DEVS paradigm to implement a simulated processor
This work is devoted to present the design and implementation of Alfa-1, a simulated computer with educational purposes. The DEVS formalism was used to attack the complexity of the design, allowing the definition of individual components that can be lately integrated into a modelling hierarchy. The...
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| Autores principales: | Daicz, S., Tróccoli, A., Zlotnik, S., Wainer, G. |
|---|---|
| Formato: | JOUR |
| Materias: | |
| Acceso en línea: | http://hdl.handle.net/20.500.12110/paper_02724715_v_n_p58_Daicz |
| Aporte de: |
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