A co-design methodology for processor-centric embedded systems with hardware acceleration using FPGA

In this work a co-design flow for processor centric embedded systems with hardware acceleration using FPGAs is proposed. This flow helps to reduce design effort by raising abstraction level while not imposing the need for engineers to learn new languages and tools. The whole system is designed using...

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Autor principal:	Pedre, Sol
Publicado:	2012
Materias:	Abstraction level Co-design flow Co-design methodology Code line Design approaches Design effort Design method Exact methods Hardware acceleration Hardware implementations Hardware-accelerated High-level modeling Multiple robot Profiling tools Real-time image processing Reference models Software coding Software domains Software solution Design Embedded software Embedded systems Engineers Image processing Robot applications Hardware
Acceso en línea:	https://bibliotecadigital.exactas.uba.ar/collection/paper/document/paper_97814673_v_n_p_Pedre http://hdl.handle.net/20.500.12110/paper_97814673_v_n_p_Pedre
Aporte de:	Biblioteca Digital - Facultad de Ciencias Exactas y Naturales (UBA) de Universidad de Buenos Aires

id	paper:paper_97814673_v_n_p_Pedre
record_format	dspace
spelling	paper:paper_97814673_v_n_p_Pedre2023-06-08T16:37:42Z A co-design methodology for processor-centric embedded systems with hardware acceleration using FPGA Pedre, Sol Abstraction level Co-design flow Co-design methodology Code line Design approaches Design effort Design method Exact methods Hardware acceleration Hardware implementations Hardware-accelerated High-level modeling Multiple robot Profiling tools Real-time image processing Reference models Software coding Software domains Software solution Design Embedded software Embedded systems Engineers Image processing Robot applications Hardware In this work a co-design flow for processor centric embedded systems with hardware acceleration using FPGAs is proposed. This flow helps to reduce design effort by raising abstraction level while not imposing the need for engineers to learn new languages and tools. The whole system is designed using well established high level modeling techniques, languages and tools from the software domain. That is, an OOP design approach expressed in UML and implemented in C++. Software coding effort is reduced since the C++ implementation not only provides a golden reference model, but may also be used as part of the final embedded software. Hardware coding effort is also reduced. The modular OOP design facilitates the engineer to find the exact methods that need to be accelerated by hardware using profiling tools, preventing useless translations to hardware. Moreover, the two-process structured VHDL design method used for hardware implementation has proven to reduce man-years, code lines and bugs in many major developments. A real-time image processing application for multiple robot localization is presented as a case study. The overall time improvement from the original software solution to the final hardware accelerated solution is 9.7x, with only 4% increase in area (143 extra slices). The embedded solution achieved following the proposed methodology runs 17% faster than in a standard PC, and it is a much smaller, cheaper and less power-consuming solution. © 2012 IEEE. Fil:Pedre, S. Universidad de Buenos Aires. Facultad de Ciencias Exactas y Naturales; Argentina. 2012 https://bibliotecadigital.exactas.uba.ar/collection/paper/document/paper_97814673_v_n_p_Pedre http://hdl.handle.net/20.500.12110/paper_97814673_v_n_p_Pedre
institution	Universidad de Buenos Aires
institution_str	I-28
repository_str	R-134
collection	Biblioteca Digital - Facultad de Ciencias Exactas y Naturales (UBA)
topic	Abstraction level Co-design flow Co-design methodology Code line Design approaches Design effort Design method Exact methods Hardware acceleration Hardware implementations Hardware-accelerated High-level modeling Multiple robot Profiling tools Real-time image processing Reference models Software coding Software domains Software solution Design Embedded software Embedded systems Engineers Image processing Robot applications Hardware
spellingShingle	Abstraction level Co-design flow Co-design methodology Code line Design approaches Design effort Design method Exact methods Hardware acceleration Hardware implementations Hardware-accelerated High-level modeling Multiple robot Profiling tools Real-time image processing Reference models Software coding Software domains Software solution Design Embedded software Embedded systems Engineers Image processing Robot applications Hardware Pedre, Sol A co-design methodology for processor-centric embedded systems with hardware acceleration using FPGA
topic_facet	Abstraction level Co-design flow Co-design methodology Code line Design approaches Design effort Design method Exact methods Hardware acceleration Hardware implementations Hardware-accelerated High-level modeling Multiple robot Profiling tools Real-time image processing Reference models Software coding Software domains Software solution Design Embedded software Embedded systems Engineers Image processing Robot applications Hardware
description	In this work a co-design flow for processor centric embedded systems with hardware acceleration using FPGAs is proposed. This flow helps to reduce design effort by raising abstraction level while not imposing the need for engineers to learn new languages and tools. The whole system is designed using well established high level modeling techniques, languages and tools from the software domain. That is, an OOP design approach expressed in UML and implemented in C++. Software coding effort is reduced since the C++ implementation not only provides a golden reference model, but may also be used as part of the final embedded software. Hardware coding effort is also reduced. The modular OOP design facilitates the engineer to find the exact methods that need to be accelerated by hardware using profiling tools, preventing useless translations to hardware. Moreover, the two-process structured VHDL design method used for hardware implementation has proven to reduce man-years, code lines and bugs in many major developments. A real-time image processing application for multiple robot localization is presented as a case study. The overall time improvement from the original software solution to the final hardware accelerated solution is 9.7x, with only 4% increase in area (143 extra slices). The embedded solution achieved following the proposed methodology runs 17% faster than in a standard PC, and it is a much smaller, cheaper and less power-consuming solution. © 2012 IEEE.
author	Pedre, Sol
author_facet	Pedre, Sol
author_sort	Pedre, Sol
title	A co-design methodology for processor-centric embedded systems with hardware acceleration using FPGA
title_short	A co-design methodology for processor-centric embedded systems with hardware acceleration using FPGA
title_full	A co-design methodology for processor-centric embedded systems with hardware acceleration using FPGA
title_fullStr	A co-design methodology for processor-centric embedded systems with hardware acceleration using FPGA
title_full_unstemmed	A co-design methodology for processor-centric embedded systems with hardware acceleration using FPGA
title_sort	co-design methodology for processor-centric embedded systems with hardware acceleration using fpga
publishDate	2012
url	https://bibliotecadigital.exactas.uba.ar/collection/paper/document/paper_97814673_v_n_p_Pedre http://hdl.handle.net/20.500.12110/paper_97814673_v_n_p_Pedre
work_keys_str_mv	AT pedresol acodesignmethodologyforprocessorcentricembeddedsystemswithhardwareaccelerationusingfpga AT pedresol codesignmethodologyforprocessorcentricembeddedsystemswithhardwareaccelerationusingfpga
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A co-design methodology for processor-centric embedded systems with hardware acceleration using FPGA

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