Design of complementary low-power CMOS architectures for looser-take-all and winner-take-all
A novel architecture for winner-take-all (WTA) and looser-take-all (LTA) circuits is proposed. As compared with other realisations, the LTA does not require input subtraction from a reference, which decreases accuracy and input dynamics. The architectures have been designed using the gm/ID methodolo...
Guardado en:
| Autores principales: | , , |
|---|---|
| Formato: | Documento de conferencia |
| Lenguaje: | Español |
| Publicado: |
1999
|
| Materias: | |
| Acceso en línea: | http://pa.bibdigital.ucc.edu.ar/3733/1/DC_Donckers_Dualibe_Verleysen.pdf |
| Aporte de: |
| Sumario: | A novel architecture for winner-take-all (WTA) and looser-take-all (LTA) circuits is proposed. As compared with other realisations, the LTA does not require input subtraction from a reference, which decreases accuracy and input dynamics. The architectures have been designed using the gm/ID methodology. It is shown that this method allows a rapid new dimensioning when specifications are modified. Both the WTA and the LTA can operate with low voltage supply, and show better speed characteristics (delay and rise time) for a 6 bits accuracy and a typical consumption of 50 μW/cell than previous realisations. © 1999 IEEE. |
|---|