Design of complementary low-power CMOS architectures for looser-take-all and winner-take-all

A novel architecture for winner-take-all (WTA) and looser-take-all (LTA) circuits is proposed. As compared with other realisations, the LTA does not require input subtraction from a reference, which decreases accuracy and input dynamics. The architectures have been designed using the gm/ID methodolo...

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Autores principales: Donckers, N., Dualibe, Fortunato Carlos Augusto, Verleysen, Michel
Formato: Documento de conferencia acceptedVersion
Lenguaje:Español
Publicado: 1999
Materias:
TK ingeniería eléctrica. Ingeniería electrónica nuclear
Acceso en línea:http://pa.bibdigital.ucc.edu.ar/3733/1/DC_Donckers_Dualibe_Verleysen.pdf
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Producción Académica Universidad Católica de Córdoba (UCCor) de Universidad Católica de Córdoba
id I38-R144-3733
record_format dspace
spelling I38-R144-37332023-06-28T17:30:23Z http://pa.bibdigital.ucc.edu.ar/3733/ Design of complementary low-power CMOS architectures for looser-take-all and winner-take-all Donckers, N. Dualibe, Fortunato Carlos Augusto Verleysen, Michel TK ingeniería eléctrica. Ingeniería electrónica nuclear A novel architecture for winner-take-all (WTA) and looser-take-all (LTA) circuits is proposed. As compared with other realisations, the LTA does not require input subtraction from a reference, which decreases accuracy and input dynamics. The architectures have been designed using the gm/ID methodology. It is shown that this method allows a rapid new dimensioning when specifications are modified. Both the WTA and the LTA can operate with low voltage supply, and show better speed characteristics (delay and rise time) for a 6 bits accuracy and a typical consumption of 50 μW/cell than previous realisations. © 1999 IEEE. 1999-04-07 application/pdf spa http://pa.bibdigital.ucc.edu.ar/3733/1/DC_Donckers_Dualibe_Verleysen.pdf Donckers, N., Dualibe, Fortunato Carlos Augusto ORCID: https://orcid.org/0000-0002-2889-315X <https://orcid.org/0000-0002-2889-315X> and Verleysen, Michel ORCID: https://orcid.org/0000-0003-4366-6155 <https://orcid.org/0000-0003-4366-6155> (1999) Design of complementary low-power CMOS architectures for looser-take-all and winner-take-all. In: International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, MicroNeuro, 7 al 9 de abril de 1999, Granada. info:eu-repo/semantics/altIdentifier/doi/10.1109/MN.1999.758887 info:eu-repo/semantics/conferenceObject info:ar-repo/semantics/documento de conferencia info:eu-repo/semantics/acceptedVersion Fil: Donckers, N. Universite Catholique de Louvain. Microelectronics Laboratory; Belgium Fil: Dualibe, C. Universidad Católica de Córdoba. Facultad de Ingeniería; Argentina Fil: Verleysen, M. Universite Catholique de Louvain. Microelectronics Laboratory; Belgium info:eu-repo/semantics/openAccess https://creativecommons.org/licenses/by-nc-nd/4.0/deed.es
institution Universidad Católica de Córdoba
institution_str I-38
repository_str R-144
collection Producción Académica Universidad Católica de Córdoba (UCCor)
language Español
orig_language_str_mv spa
topic TK ingeniería eléctrica. Ingeniería electrónica nuclear
spellingShingle TK ingeniería eléctrica. Ingeniería electrónica nuclear
Donckers, N.
Dualibe, Fortunato Carlos Augusto
Verleysen, Michel
Design of complementary low-power CMOS architectures for looser-take-all and winner-take-all
topic_facet TK ingeniería eléctrica. Ingeniería electrónica nuclear
description A novel architecture for winner-take-all (WTA) and looser-take-all (LTA) circuits is proposed. As compared with other realisations, the LTA does not require input subtraction from a reference, which decreases accuracy and input dynamics. The architectures have been designed using the gm/ID methodology. It is shown that this method allows a rapid new dimensioning when specifications are modified. Both the WTA and the LTA can operate with low voltage supply, and show better speed characteristics (delay and rise time) for a 6 bits accuracy and a typical consumption of 50 μW/cell than previous realisations. © 1999 IEEE.
format Documento de conferencia
Documento de conferencia
acceptedVersion
author Donckers, N.
Dualibe, Fortunato Carlos Augusto
Verleysen, Michel
author_facet Donckers, N.
Dualibe, Fortunato Carlos Augusto
Verleysen, Michel
author_sort Donckers, N.
title Design of complementary low-power CMOS architectures for looser-take-all and winner-take-all
title_short Design of complementary low-power CMOS architectures for looser-take-all and winner-take-all
title_full Design of complementary low-power CMOS architectures for looser-take-all and winner-take-all
title_fullStr Design of complementary low-power CMOS architectures for looser-take-all and winner-take-all
title_full_unstemmed Design of complementary low-power CMOS architectures for looser-take-all and winner-take-all
title_sort design of complementary low-power cmos architectures for looser-take-all and winner-take-all
publishDate 1999
url http://pa.bibdigital.ucc.edu.ar/3733/1/DC_Donckers_Dualibe_Verleysen.pdf
work_keys_str_mv AT donckersn designofcomplementarylowpowercmosarchitecturesforloosertakeallandwinnertakeall
AT dualibefortunatocarlosaugusto designofcomplementarylowpowercmosarchitecturesforloosertakeallandwinnertakeall
AT verleysenmichel designofcomplementarylowpowercmosarchitecturesforloosertakeallandwinnertakeall
_version_ 1769989558680682496

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