Low Area Implementation of the Advanced Encryption Standard with Counter Mode for System-On-Chip - FPGA

Cryptography plays a crucial role in protecting information on public networks. The implementation of AES with CTR on Xilinx SoC-FPGA devices, such as Zynq 7000 and Kintex 7, aims to enhance security in IoT devices and embedded systems. The goal is to ensure data confidentiality and availability in...

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Autores principales: Paz Penagos, Hernan, Paipilla Arenas, Arthur Stink, Ortiz Niño, Marco Andrés
Formato: Artículo publishedVersion
Lenguaje:Inglés
Publicado: FIUBA 2024
Materias:
advanced encryption standard (AES)
counter mode (CTR)
field programable gate array (FPGA)
System on Chip (SoC)
Zynq7000
Xilinx
Estándar de Cifrado Avanzado
CTR
Arreglo de compuertas programables de campo
Sistema en Chip (SoC)
Zynq 7000
Acceso en línea:https://elektron.fi.uba.ar/elektron/article/view/201
https://repositoriouba.sisbi.uba.ar/gsdl/cgi-bin/library.cgi?a=d&c=elektron&d=201_oai
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Repositorio Digital de la Universidad de Buenos Aires (UBA) de Universidad de Buenos Aires
id I28-R145-201_oai
record_format dspace
spelling I28-R145-201_oai2026-02-11 Paz Penagos, Hernan Paipilla Arenas, Arthur Stink Ortiz Niño, Marco Andrés 2024-12-15 Cryptography plays a crucial role in protecting information on public networks. The implementation of AES with CTR on Xilinx SoC-FPGA devices, such as Zynq 7000 and Kintex 7, aims to enhance security in IoT devices and embedded systems. The goal is to ensure data confidentiality and availability in connected environments, prioritizing low area usage, low power consumption, and high performance. Implementation was made using a Very High-Speed Integrated Circuit Hardware Description Language (VHDL) on Vivado 2019-2. The results show its area utilization for AES and AES-CTR implementations, with a throughput of 1.8 and 7.67 Gbps for Zynq 7000 and, 2.72 and 11.11 Gbps for Kintex 7; they are also presented for a 128-bits key size and four CTR blocks. VHDL generics can be configured to be 192-bit and 256-bit lengths with different block sizes. Implemented AES-CTR IP showed correct behavior for 128, 192, and 256 key sizes with four CTR blocks. A cipher process with sizes 192 and 256 requires additional cycles that affect the timing performance and hardware utilization. La criptografía juega un papel crucial en la protección de la información en redes públicas. La implementación de AES con CTR en dispositivos SoC-FPGA de Xilinx, como Zynq 7000 y Kintex 7, busca mejorar la seguridad en dispositivos IoT y sistemas embebidos. El objetivo es garantizar la confidencialidad y disponibilidad de los datos en entornos conectados, priorizando un bajo uso de área, bajo consumo de energía y alto rendimiento. La implementación se realizó utilizando el lenguaje de descripción de hardware VHDL en Vivado 2019-2. Los resultados muestran la utilización de área para las implementaciones de AES y AES-CTR, con un rendimiento de 1.8 y 7.67 Gbps para Zynq 7000 y de 2.72 y 11.11 Gbps para Kintex 7; también se presentan para una clave de 128 bits y cuatro bloques CTR. Los genéricos en VHDL pueden configurarse para longitudes de 192 bits y 256 bits con diferentes tamaños de bloque. El IP implementado de AES-CTR mostró un comportamiento correcto para tamaños de clave de 128, 192 y 56 bits con cuatro bloques CTR. Un proceso de cifrado con tamaños de 192 y 256 bits requiere ciclos adicionales que afectan el rendimiento temporal y la utilización de hardware. application/pdf text/html https://elektron.fi.uba.ar/elektron/article/view/201 10.37537/rev.elektron.8.2.201.2024 eng FIUBA https://elektron.fi.uba.ar/elektron/article/view/201/358 https://elektron.fi.uba.ar/elektron/article/view/201/370 Derechos de autor 2024 Hernan Paz Penagos, Arthur Stink Paipilla Arenas, Marco Andrés Ortiz Niño Elektron Journal; Vol. 8 No. 2 (2024); 71-76 Revista Elektron; Vol. 8 Núm. 2 (2024); 71-76 Revista Elektron; v. 8 n. 2 (2024); 71-76 2525-0159 2525-0159 advanced encryption standard (AES) counter mode (CTR) field programable gate array (FPGA) System on Chip (SoC) Zynq7000 Xilinx Estándar de Cifrado Avanzado CTR Arreglo de compuertas programables de campo Sistema en Chip (SoC) Zynq 7000 Xilinx Low Area Implementation of the Advanced Encryption Standard with Counter Mode for System-On-Chip - FPGA Implementación de un cifrado avanzado con modo contador para sistema en chip FPGA de área pequeña info:eu-repo/semantics/article info:eu-repo/semantics/publishedVersion https://repositoriouba.sisbi.uba.ar/gsdl/cgi-bin/library.cgi?a=d&c=elektron&d=201_oai
institution Universidad de Buenos Aires
institution_str I-28
repository_str R-145
collection Repositorio Digital de la Universidad de Buenos Aires (UBA)
language Inglés
orig_language_str_mv eng
topic advanced encryption standard (AES)
counter mode (CTR)
field programable gate array (FPGA)
System on Chip (SoC)
Zynq7000
Xilinx
Estándar de Cifrado Avanzado
CTR
Arreglo de compuertas programables de campo
Sistema en Chip (SoC)
Zynq 7000
Xilinx
spellingShingle advanced encryption standard (AES)
counter mode (CTR)
field programable gate array (FPGA)
System on Chip (SoC)
Zynq7000
Xilinx
Estándar de Cifrado Avanzado
CTR
Arreglo de compuertas programables de campo
Sistema en Chip (SoC)
Zynq 7000
Xilinx
Paz Penagos, Hernan
Paipilla Arenas, Arthur Stink
Ortiz Niño, Marco Andrés
Low Area Implementation of the Advanced Encryption Standard with Counter Mode for System-On-Chip - FPGA
topic_facet advanced encryption standard (AES)
counter mode (CTR)
field programable gate array (FPGA)
System on Chip (SoC)
Zynq7000
Xilinx
Estándar de Cifrado Avanzado
CTR
Arreglo de compuertas programables de campo
Sistema en Chip (SoC)
Zynq 7000
Xilinx
description Cryptography plays a crucial role in protecting information on public networks. The implementation of AES with CTR on Xilinx SoC-FPGA devices, such as Zynq 7000 and Kintex 7, aims to enhance security in IoT devices and embedded systems. The goal is to ensure data confidentiality and availability in connected environments, prioritizing low area usage, low power consumption, and high performance. Implementation was made using a Very High-Speed Integrated Circuit Hardware Description Language (VHDL) on Vivado 2019-2. The results show its area utilization for AES and AES-CTR implementations, with a throughput of 1.8 and 7.67 Gbps for Zynq 7000 and, 2.72 and 11.11 Gbps for Kintex 7; they are also presented for a 128-bits key size and four CTR blocks. VHDL generics can be configured to be 192-bit and 256-bit lengths with different block sizes. Implemented AES-CTR IP showed correct behavior for 128, 192, and 256 key sizes with four CTR blocks. A cipher process with sizes 192 and 256 requires additional cycles that affect the timing performance and hardware utilization.
format Artículo
publishedVersion
author Paz Penagos, Hernan
Paipilla Arenas, Arthur Stink
Ortiz Niño, Marco Andrés
author_facet Paz Penagos, Hernan
Paipilla Arenas, Arthur Stink
Ortiz Niño, Marco Andrés
author_sort Paz Penagos, Hernan
title Low Area Implementation of the Advanced Encryption Standard with Counter Mode for System-On-Chip - FPGA
title_short Low Area Implementation of the Advanced Encryption Standard with Counter Mode for System-On-Chip - FPGA
title_full Low Area Implementation of the Advanced Encryption Standard with Counter Mode for System-On-Chip - FPGA
title_fullStr Low Area Implementation of the Advanced Encryption Standard with Counter Mode for System-On-Chip - FPGA
title_full_unstemmed Low Area Implementation of the Advanced Encryption Standard with Counter Mode for System-On-Chip - FPGA
title_sort low area implementation of the advanced encryption standard with counter mode for system-on-chip - fpga
publisher FIUBA
publishDate 2024
url https://elektron.fi.uba.ar/elektron/article/view/201
https://repositoriouba.sisbi.uba.ar/gsdl/cgi-bin/library.cgi?a=d&c=elektron&d=201_oai
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