FPGA Algorithm Implementation for Parasitic Analysis
An efficient parasite control reduces significant losses in the agribusiness, but current methods involve costs and delays. Therefore, the development of a portable device to automates this task is proposed. This work presents a hardware implementation of an automatic parasite egg counting algorithm...
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| Autores principales: | , , , , , |
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| Formato: | Artículo publishedVersion |
| Lenguaje: | Español |
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FIUBA
2022
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| Materias: | |
| Acceso en línea: | http://elektron.fi.uba.ar/index.php/elektron/article/view/149 http://repositoriouba.sisbi.uba.ar/gsdl/cgi-bin/library.cgi?a=d&c=elektron&d=149_oai |
| Aporte de: |
| Sumario: | An efficient parasite control reduces significant losses in the agribusiness, but current methods involve costs and delays. Therefore, the development of a portable device to automates this task is proposed. This work presents a hardware implementation of an automatic parasite egg counting algorithm using high-level synthesis. The results demonstrate the feasibility of the implementation, with an 87% accuracy operating at a rate of up to 65 frames per second and an occupation of LUTs less than 45%, considering two commercial kits (PYNQ-Z1 and ULTRA96V2). |
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