FPGA Algorithm Implementation for Parasitic Analysis

An efficient parasite control reduces significant losses in the agribusiness, but current methods involve costs and delays. Therefore, the development of a portable device to automates this task is proposed. This work presents a hardware implementation of an automatic parasite egg counting algorithm...

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Autores principales: Rombolá, Guido, Leiva, Lucas, Vázquez, Martín, Toloza, Juan, Sagües, Federica, Saumell, Carlos
Formato: Artículo publishedVersion
Lenguaje:Español
Publicado: FIUBA 2022
Materias:
Parasitic Analysis; Image Processing; HLS; FPGA
Análisis Parasitario; Procesamiento de Imágenes; HLS; FPGA
Acceso en línea:http://elektron.fi.uba.ar/index.php/elektron/article/view/149
http://repositoriouba.sisbi.uba.ar/gsdl/cgi-bin/library.cgi?a=d&c=elektron&d=149_oai
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Repositorio Digital de la Universidad de Buenos Aires (UBA) de Universidad de Buenos Aires
id I28-R145-149_oai
record_format dspace
spelling I28-R145-149_oai2022-09-23 Rombolá, Guido Leiva, Lucas Vázquez, Martín Toloza, Juan Sagües, Federica Saumell, Carlos 2022-06-15 An efficient parasite control reduces significant losses in the agribusiness, but current methods involve costs and delays. Therefore, the development of a portable device to automates this task is proposed. This work presents a hardware implementation of an automatic parasite egg counting algorithm using high-level synthesis. The results demonstrate the feasibility of the implementation, with an 87% accuracy operating at a rate of up to 65 frames per second and an occupation of LUTs less than 45%, considering two commercial kits (PYNQ-Z1 and ULTRA96V2). Un control parasitario eficiente permite reducir pérdidas significativas en la agroindustria. Los métodos actuales con los que se realiza este tipo de controles imponen costos y demoras. Por ello, se propone el desarrollo de un dispositivo portátil que automatice esta tarea. En este trabajo se presenta la implementación hardware de un algoritmo de conteo automático de huevos de parásitos utilizando síntesis de alto nivel. Los resultados demuestran la factibilidad de la implementación, con un 87% de precisión operando a una tasa de hasta de 65 frames por segundo y una ocupación de LUTs menor al 45%, considerando dos kits comerciales (PYNQ-Z1 y ULTRA96V2). application/pdf text/html http://elektron.fi.uba.ar/index.php/elektron/article/view/149 10.37537/rev.elektron.6.1.149.2022 spa FIUBA http://elektron.fi.uba.ar/index.php/elektron/article/view/149/281 http://elektron.fi.uba.ar/index.php/elektron/article/view/149/290 http://elektron.fi.uba.ar/index.php/elektron/article/downloadSuppFile/149/172 http://elektron.fi.uba.ar/index.php/elektron/article/downloadSuppFile/149/181 Copyright (c) 2022 Guido Rombolá, Lucas Leiva, Martín Vázquez, Juan Toloza, Federica Sagües, Carlos Saumell http://creativecommons.org/licenses/by-nc-nd/4.0 Elektron; Vol 6, No 1 (2022); 36-40 Elektron; Vol 6, No 1 (2022); 36-40 2525-0159 Parasitic Analysis; Image Processing; HLS; FPGA Análisis Parasitario; Procesamiento de Imágenes; HLS; FPGA FPGA Algorithm Implementation for Parasitic Analysis Implementación en FPGA de algoritmo para análisis parasitario info:eu-repo/semantics/article info:eu-repo/semantics/publishedVersion http://repositoriouba.sisbi.uba.ar/gsdl/cgi-bin/library.cgi?a=d&c=elektron&d=149_oai
institution Universidad de Buenos Aires
institution_str I-28
repository_str R-145
collection Repositorio Digital de la Universidad de Buenos Aires (UBA)
language Español
orig_language_str_mv spa
topic Parasitic Analysis; Image Processing; HLS; FPGA
Análisis Parasitario; Procesamiento de Imágenes; HLS; FPGA
spellingShingle Parasitic Analysis; Image Processing; HLS; FPGA
Análisis Parasitario; Procesamiento de Imágenes; HLS; FPGA
Rombolá, Guido
Leiva, Lucas
Vázquez, Martín
Toloza, Juan
Sagües, Federica
Saumell, Carlos
FPGA Algorithm Implementation for Parasitic Analysis
topic_facet Parasitic Analysis; Image Processing; HLS; FPGA
Análisis Parasitario; Procesamiento de Imágenes; HLS; FPGA
description An efficient parasite control reduces significant losses in the agribusiness, but current methods involve costs and delays. Therefore, the development of a portable device to automates this task is proposed. This work presents a hardware implementation of an automatic parasite egg counting algorithm using high-level synthesis. The results demonstrate the feasibility of the implementation, with an 87% accuracy operating at a rate of up to 65 frames per second and an occupation of LUTs less than 45%, considering two commercial kits (PYNQ-Z1 and ULTRA96V2).
format Artículo
publishedVersion
author Rombolá, Guido
Leiva, Lucas
Vázquez, Martín
Toloza, Juan
Sagües, Federica
Saumell, Carlos
author_facet Rombolá, Guido
Leiva, Lucas
Vázquez, Martín
Toloza, Juan
Sagües, Federica
Saumell, Carlos
author_sort Rombolá, Guido
title FPGA Algorithm Implementation for Parasitic Analysis
title_short FPGA Algorithm Implementation for Parasitic Analysis
title_full FPGA Algorithm Implementation for Parasitic Analysis
title_fullStr FPGA Algorithm Implementation for Parasitic Analysis
title_full_unstemmed FPGA Algorithm Implementation for Parasitic Analysis
title_sort fpga algorithm implementation for parasitic analysis
publisher FIUBA
publishDate 2022
url http://elektron.fi.uba.ar/index.php/elektron/article/view/149
http://repositoriouba.sisbi.uba.ar/gsdl/cgi-bin/library.cgi?a=d&c=elektron&d=149_oai
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AT leivalucas fpgaalgorithmimplementationforparasiticanalysis
AT vazquezmartin fpgaalgorithmimplementationforparasiticanalysis
AT tolozajuan fpgaalgorithmimplementationforparasiticanalysis
AT saguesfederica fpgaalgorithmimplementationforparasiticanalysis
AT saumellcarlos fpgaalgorithmimplementationforparasiticanalysis
AT rombolaguido implementacionenfpgadealgoritmoparaanalisisparasitario
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AT tolozajuan implementacionenfpgadealgoritmoparaanalisisparasitario
AT saguesfederica implementacionenfpgadealgoritmoparaanalisisparasitario
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