A Comparative Study between HLS and HDL on SoC for Image Processing Applications

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The increasing complexity in today’s systems and the limited market times demand new development tools for FPGA. Currently, in addition to traditional hardware description languages (HDLs), there are high level synthesis (HLS) tools that increase the abstraction level in system development. Despite...

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Autores principales: Millón, Roberto, Frati, Emmanuel, Rucci, Enzo
Formato: Artículo publishedVersion
Lenguaje:Inglés
Publicado: FIUBA 2020
Materias:
FPGA; SoC; HDL; HLS; Sobel
FPGA; SoC; Sobel; HDL; HLS
Acceso en línea:http://elektron.fi.uba.ar/index.php/elektron/article/view/117
http://repositoriouba.sisbi.uba.ar/gsdl/cgi-bin/library.cgi?a=d&c=elektron&d=117_oai
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Repositorio Digital de la Universidad de Buenos Aires (UBA) de Universidad de Buenos Aires
id I28-R145-117_oai
record_format dspace
spelling I28-R145-117_oai2021-03-16 Millón, Roberto Frati, Emmanuel Rucci, Enzo 2020-12-14 The increasing complexity in today’s systems and the limited market times demand new development tools for FPGA. Currently, in addition to traditional hardware description languages (HDLs), there are high level synthesis (HLS) tools that increase the abstraction level in system development. Despite the greater simplicity of design and testing, HLS has some drawbacks in describing hardware. This paper presents a comparative study between HLS and HDL for FPGA, using a Sobel filter as a case study in the image processing field. The results show that the HDL implementation is slightly better than the HLS version considering resource usage and response time. However, the programming effort required in the HDL solution is significantly larger than in the HLS counterpart. La creciente complejidad de los sistemas actuales y los tiempos limitados del mercado exigen nuevas herramientas de desarrollo para las FPGAs. Hoy en día, además de los tradicionales lenguajes de descripción de hardware (HDL), existen herramientas de síntesis de alto nivel (HLS) que aumentan el nivel de abstracción en el desarrollo de sistemas. A pesar de la mayor simplicidad de diseño y pruebas, HLS tiene algunos inconvenientes para describir hardware. Este documento presenta un estudio comparativo entre HLS y HDL para FPGA, utilizando un filtro Sobel como caso de estudio en el ámbito del procesamiento de imágenes. Los resultados muestran que la implementación HDL es levemente mejor que la versión HLS considerando uso de recursos y tiempo de respuesta. Sin embargo, el esfuerzo de programación en la implementación de HDL es significativamente mayor. application/pdf text/html http://elektron.fi.uba.ar/index.php/elektron/article/view/117 10.37537/rev.elektron.4.2.117.2020 eng FIUBA http://elektron.fi.uba.ar/index.php/elektron/article/view/117/207 http://elektron.fi.uba.ar/index.php/elektron/article/view/117/219 http://elektron.fi.uba.ar/index.php/elektron/article/downloadSuppFile/117/103 http://elektron.fi.uba.ar/index.php/elektron/article/downloadSuppFile/117/104 Copyright (c) 2020 Enzo Rucci http://creativecommons.org/licenses/by-nc-nd/4.0 Elektron; Vol 4, No 2 (2020); 100-106 Elektron; Vol 4, No 2 (2020); 100-106 2525-0159 FPGA; SoC; HDL; HLS; Sobel FPGA; SoC; Sobel; HDL; HLS A Comparative Study between HLS and HDL on SoC for Image Processing Applications Un estudio comparativo entre HLS y HDL en SoC para aplicaciones de procesamiento de imágenes info:eu-repo/semantics/article info:eu-repo/semantics/publishedVersion http://repositoriouba.sisbi.uba.ar/gsdl/cgi-bin/library.cgi?a=d&c=elektron&d=117_oai
institution Universidad de Buenos Aires
institution_str I-28
repository_str R-145
collection Repositorio Digital de la Universidad de Buenos Aires (UBA)
language Inglés
orig_language_str_mv eng
topic FPGA; SoC; HDL; HLS; Sobel
FPGA; SoC; Sobel; HDL; HLS
spellingShingle FPGA; SoC; HDL; HLS; Sobel
FPGA; SoC; Sobel; HDL; HLS
Millón, Roberto
Frati, Emmanuel
Rucci, Enzo
A Comparative Study between HLS and HDL on SoC for Image Processing Applications
topic_facet FPGA; SoC; HDL; HLS; Sobel
FPGA; SoC; Sobel; HDL; HLS
description The increasing complexity in today’s systems and the limited market times demand new development tools for FPGA. Currently, in addition to traditional hardware description languages (HDLs), there are high level synthesis (HLS) tools that increase the abstraction level in system development. Despite the greater simplicity of design and testing, HLS has some drawbacks in describing hardware. This paper presents a comparative study between HLS and HDL for FPGA, using a Sobel filter as a case study in the image processing field. The results show that the HDL implementation is slightly better than the HLS version considering resource usage and response time. However, the programming effort required in the HDL solution is significantly larger than in the HLS counterpart.
format Artículo
publishedVersion
author Millón, Roberto
Frati, Emmanuel
Rucci, Enzo
author_facet Millón, Roberto
Frati, Emmanuel
Rucci, Enzo
author_sort Millón, Roberto
title A Comparative Study between HLS and HDL on SoC for Image Processing Applications
title_short A Comparative Study between HLS and HDL on SoC for Image Processing Applications
title_full A Comparative Study between HLS and HDL on SoC for Image Processing Applications
title_fullStr A Comparative Study between HLS and HDL on SoC for Image Processing Applications
title_full_unstemmed A Comparative Study between HLS and HDL on SoC for Image Processing Applications
title_sort comparative study between hls and hdl on soc for image processing applications
publisher FIUBA
publishDate 2020
url http://elektron.fi.uba.ar/index.php/elektron/article/view/117
http://repositoriouba.sisbi.uba.ar/gsdl/cgi-bin/library.cgi?a=d&c=elektron&d=117_oai
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