Memory disambiguation hardware: a review
One of the main challenges of modern processor designs is the implementation of scalable and efficient mechanisms to detect memory access order violations as a result of out-of-order execution. Conventional structures performing this task are complex, inefficient and power-hungry. This fact has gen...
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| Autores principales: | , , , , |
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| Formato: | Articulo |
| Lenguaje: | Inglés |
| Publicado: |
2008
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| Materias: | |
| Acceso en línea: | http://sedici.unlp.edu.ar/handle/10915/9636 http://journal.info.unlp.edu.ar/wp-content/uploads/JCST-Oct08-1.pdf |
| Aporte de: |
| Sumario: | One of the main challenges of modern processor designs is the implementation of scalable and efficient mechanisms to detect memory access order violations as a result of out-of-order execution. Conventional structures performing this task are complex, inefficient and power-hungry.
This fact has generated a large body of work on optimizing address-based memory disambiguation logic, namely the load-store queue. In this paper we review the most significant proposals in this research field, focusing on our own contributions. |
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