Implementation of high-speed fixed-point dividers on FPGA

Study deals with implementations of fixed-point division modules based on different algorithms on basis of Xilinx FPGAs. We show that our implementation of the nonrestoring algorithm is significantly faster and smaller than the 32-bit IP Core "Pipelined Divider" from Xilinx. For example, t...

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Detalles Bibliográficos
Autor principal: Sorokin, Nikolai
Formato: Articulo
Lenguaje:Inglés
Publicado: 2006
Materias:
Ciencias Informáticas
modular design
programmable logic
Acceso en línea:http://sedici.unlp.edu.ar/handle/10915/9513
http://journal.info.unlp.edu.ar/wp-content/uploads/JCST-Apr06-2.pdf
Aporte de:
SEDICI (UNLP) de Universidad Nacional de La Plata

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