Implementation of high-speed fixed-point dividers on FPGA

Study deals with implementations of fixed-point division modules based on different algorithms on basis of Xilinx FPGAs. We show that our implementation of the nonrestoring algorithm is significantly faster and smaller than the 32-bit IP Core "Pipelined Divider" from Xilinx. For example, t...

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Detalles Bibliográficos
Autor principal: Sorokin, Nikolai
Formato: Articulo
Lenguaje:Inglés
Publicado: 2006
Materias:
Ciencias Informáticas
modular design
programmable logic
Acceso en línea:http://sedici.unlp.edu.ar/handle/10915/9513
http://journal.info.unlp.edu.ar/wp-content/uploads/JCST-Apr06-2.pdf
Aporte de:
SEDICI (UNLP) de Universidad Nacional de La Plata
id I19-R120-10915-9513
record_format dspace
institution Universidad Nacional de La Plata
institution_str I-19
repository_str R-120
collection SEDICI (UNLP)
language Inglés
topic Ciencias Informáticas
modular design
programmable logic
spellingShingle Ciencias Informáticas
modular design
programmable logic
Sorokin, Nikolai
Implementation of high-speed fixed-point dividers on FPGA
topic_facet Ciencias Informáticas
modular design
programmable logic
description Study deals with implementations of fixed-point division modules based on different algorithms on basis of Xilinx FPGAs. We show that our implementation of the nonrestoring algorithm is significantly faster and smaller than the 32-bit IP Core "Pipelined Divider" from Xilinx. For example, the speed of the 32-bit designed module is almost 245 MHz vs. 193 MHz from Xilinx divider. Moreover, high-speed parameterized modules are designed to provide arbitrary precision of the fixed-point division, for example, with 64-bit or 128-bit operands and large fixedpoint result.
format Articulo
Articulo
author Sorokin, Nikolai
author_facet Sorokin, Nikolai
author_sort Sorokin, Nikolai
title Implementation of high-speed fixed-point dividers on FPGA
title_short Implementation of high-speed fixed-point dividers on FPGA
title_full Implementation of high-speed fixed-point dividers on FPGA
title_fullStr Implementation of high-speed fixed-point dividers on FPGA
title_full_unstemmed Implementation of high-speed fixed-point dividers on FPGA
title_sort implementation of high-speed fixed-point dividers on fpga
publishDate 2006
url http://sedici.unlp.edu.ar/handle/10915/9513
http://journal.info.unlp.edu.ar/wp-content/uploads/JCST-Apr06-2.pdf
work_keys_str_mv AT sorokinnikolai implementationofhighspeedfixedpointdividersonfpga
bdutipo_str Repositorios
_version_ 1764820491252531201

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