A Fault Diagnosis Scheme and Its Quality Issue in Reconfigurable Array Architecture

In this paper, we propose an efficient diagnosis scheme to detect and locate the switching network defects/faults in reconfigurable array architecture. This diagnosis scheme performs the test of switching network based on the scan path and fault intersection test methodology to locate the faults occ...

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Detalles Bibliográficos
Autor principal: Chen, Yung-Yuan
Formato: Articulo
Lenguaje:Inglés
Publicado: 2006
Materias:
Ciencias Informáticas
Reliability, Testing, and Fault-Tolerance
Arrays
switching network
Acceso en línea:http://sedici.unlp.edu.ar/handle/10915/9511
http://journal.info.unlp.edu.ar/wp-content/uploads/JCST-Apr06-3.pdf
Aporte de:
SEDICI (UNLP) de Universidad Nacional de La Plata
id I19-R120-10915-9511
record_format dspace
institution Universidad Nacional de La Plata
institution_str I-19
repository_str R-120
collection SEDICI (UNLP)
language Inglés
topic Ciencias Informáticas
Reliability, Testing, and Fault-Tolerance
Arrays
switching network
spellingShingle Ciencias Informáticas
Reliability, Testing, and Fault-Tolerance
Arrays
switching network
Chen, Yung-Yuan
A Fault Diagnosis Scheme and Its Quality Issue in Reconfigurable Array Architecture
topic_facet Ciencias Informáticas
Reliability, Testing, and Fault-Tolerance
Arrays
switching network
description In this paper, we propose an efficient diagnosis scheme to detect and locate the switching network defects/faults in reconfigurable array architecture. This diagnosis scheme performs the test of switching network based on the scan path and fault intersection test methodology to locate the faults occurring in the switching network. After the diagnosis of switching network, the processing element (PE) test can then be initiated through the good switches and links. Errors in testing that cause a good switch, link or PE to be considered as a bad one is called "killing error". The issue of killing error in testing is addressed and the probability of killing error for our diagnosis technique is analyzed and shown to be extremely low. The significance of this approach is the ability to detect and locate the multiple faults in switches, links, and PEs with low testing circuit overhead, and to offer the good test quality in linear diagnosis time.
format Articulo
Articulo
author Chen, Yung-Yuan
author_facet Chen, Yung-Yuan
author_sort Chen, Yung-Yuan
title A Fault Diagnosis Scheme and Its Quality Issue in Reconfigurable Array Architecture
title_short A Fault Diagnosis Scheme and Its Quality Issue in Reconfigurable Array Architecture
title_full A Fault Diagnosis Scheme and Its Quality Issue in Reconfigurable Array Architecture
title_fullStr A Fault Diagnosis Scheme and Its Quality Issue in Reconfigurable Array Architecture
title_full_unstemmed A Fault Diagnosis Scheme and Its Quality Issue in Reconfigurable Array Architecture
title_sort fault diagnosis scheme and its quality issue in reconfigurable array architecture
publishDate 2006
url http://sedici.unlp.edu.ar/handle/10915/9511
http://journal.info.unlp.edu.ar/wp-content/uploads/JCST-Apr06-3.pdf
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AT chenyungyuan faultdiagnosisschemeanditsqualityissueinreconfigurablearrayarchitecture
bdutipo_str Repositorios
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