Fetch unit design for scalable simultaneous multithreading (ScSMT)

Continuous IC process enhancements make possible to integrate on a single chip the re-sources required for simultaneously executing multiple control flows or threads, exploiting different levels of thread-level parallelism: application-, function-, and loop-level. Scalable simultaneous multi-threadi...

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Detalles Bibliográficos
Autores principales: Moure, Juan Carlos, Rexachs del Rosario, Dolores, Luque Fadón, Emilio
Formato: Articulo
Lenguaje:Inglés
Publicado: 2001
Materias:
Ciencias Informáticas
Procesador paralelo
Threads
Arquitectura del procesador
Informática
Acceso en línea:http://sedici.unlp.edu.ar/handle/10915/9404
http://journal.info.unlp.edu.ar/wp-content/uploads/ipaper1.pdf
Aporte de:
SEDICI (UNLP) de Universidad Nacional de La Plata
id I19-R120-10915-9404
record_format dspace
institution Universidad Nacional de La Plata
institution_str I-19
repository_str R-120
collection SEDICI (UNLP)
language Inglés
topic Ciencias Informáticas
Procesador paralelo
Threads
Arquitectura del procesador
Informática
spellingShingle Ciencias Informáticas
Procesador paralelo
Threads
Arquitectura del procesador
Informática
Moure, Juan Carlos
Rexachs del Rosario, Dolores
Luque Fadón, Emilio
Fetch unit design for scalable simultaneous multithreading (ScSMT)
topic_facet Ciencias Informáticas
Procesador paralelo
Threads
Arquitectura del procesador
Informática
description Continuous IC process enhancements make possible to integrate on a single chip the re-sources required for simultaneously executing multiple control flows or threads, exploiting different levels of thread-level parallelism: application-, function-, and loop-level. Scalable simultaneous multi-threading combines static and dynamic mechanisms to assemble a complexity-effective design that provides high instruction per cycle rates without sacrificing cycle time nor single-thread performance. This paper addresses the design of the fetch unit for a high-performance, scalable, simultaneous multithreaded processor. We present the detailed microarchitecture of a clustered and reconfigurable fetch unit based on an existing single-thread fetch unit. In order to minimize the occurrence of fetch hazards, the fetch unit dynamically adapts to the available thread-level parallelism and to the fetch characteristics of the active threads, working as a single shared unit or as two separate clusters. It combines static and dynamic methods in a complexity-efficient way. The design is supported by a simulation- based analysis of different instruction cache and branch target buffer configurations on the context of a multithreaded execution workload. Average reductions on the miss rates between 30% and 60% and peak reductions greater than 200% are obtained.
format Articulo
Articulo
author Moure, Juan Carlos
Rexachs del Rosario, Dolores
Luque Fadón, Emilio
author_facet Moure, Juan Carlos
Rexachs del Rosario, Dolores
Luque Fadón, Emilio
author_sort Moure, Juan Carlos
title Fetch unit design for scalable simultaneous multithreading (ScSMT)
title_short Fetch unit design for scalable simultaneous multithreading (ScSMT)
title_full Fetch unit design for scalable simultaneous multithreading (ScSMT)
title_fullStr Fetch unit design for scalable simultaneous multithreading (ScSMT)
title_full_unstemmed Fetch unit design for scalable simultaneous multithreading (ScSMT)
title_sort fetch unit design for scalable simultaneous multithreading (scsmt)
publishDate 2001
url http://sedici.unlp.edu.ar/handle/10915/9404
http://journal.info.unlp.edu.ar/wp-content/uploads/ipaper1.pdf
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AT rexachsdelrosariodolores fetchunitdesignforscalablesimultaneousmultithreadingscsmt
AT luquefadonemilio fetchunitdesignforscalablesimultaneousmultithreadingscsmt
bdutipo_str Repositorios
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