Implementing an ISR defense on a MIPS architecture

Code injection attacks are an undeniable threat in today’s cyberworld. Instruction Set Randomization (ISR) was initially proposed in 2003. This technique was designed to protect systems against code injection attacks by creating an unique instruction set for each machine, thanks to randomization. It...

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Detalles Bibliográficos
Autores principales: Sanabria Sancho, Loriana, Gabriela Barrantes, Elena
Formato: Objeto de conferencia
Lenguaje:Inglés
Publicado: 2017
Materias:
Ciencias Informáticas
ISR
MIPS processor
encryption circuits
code injection attacks
Hardware
Acceso en línea:http://sedici.unlp.edu.ar/handle/10915/65514
Aporte de:
SEDICI (UNLP) de Universidad Nacional de La Plata
id I19-R120-10915-65514
record_format dspace
institution Universidad Nacional de La Plata
institution_str I-19
repository_str R-120
collection SEDICI (UNLP)
language Inglés
topic Ciencias Informáticas
ISR
MIPS processor
encryption circuits
code injection attacks
Hardware
spellingShingle Ciencias Informáticas
ISR
MIPS processor
encryption circuits
code injection attacks
Hardware
Sanabria Sancho, Loriana
Gabriela Barrantes, Elena
Implementing an ISR defense on a MIPS architecture
topic_facet Ciencias Informáticas
ISR
MIPS processor
encryption circuits
code injection attacks
Hardware
description Code injection attacks are an undeniable threat in today’s cyberworld. Instruction Set Randomization (ISR) was initially proposed in 2003. This technique was designed to protect systems against code injection attacks by creating an unique instruction set for each machine, thanks to randomization. It is a promising technique in the growing embedded system and Internet of Things (IoT) devices ecosystem, where the lack of complex memory management make these devices more vulnerable. However, most of ISR implementations up to day are entirely software based. In this work, we implement hardware support for an ISR defense on an 32 bits, 5 pipeline stages MIPS processor (which is an embedded system compatible architecture). Two obfuscation schemes were implemented, one based on XOR encryption and the other on transposition. The hardware implementation was tested under synthetic code injection attacks and results shows the effectiveness of the defense using both encryption circuits.
format Objeto de conferencia
Objeto de conferencia
author Sanabria Sancho, Loriana
Gabriela Barrantes, Elena
author_facet Sanabria Sancho, Loriana
Gabriela Barrantes, Elena
author_sort Sanabria Sancho, Loriana
title Implementing an ISR defense on a MIPS architecture
title_short Implementing an ISR defense on a MIPS architecture
title_full Implementing an ISR defense on a MIPS architecture
title_fullStr Implementing an ISR defense on a MIPS architecture
title_full_unstemmed Implementing an ISR defense on a MIPS architecture
title_sort implementing an isr defense on a mips architecture
publishDate 2017
url http://sedici.unlp.edu.ar/handle/10915/65514
work_keys_str_mv AT sanabriasancholoriana implementinganisrdefenseonamipsarchitecture
AT gabrielabarranteselena implementinganisrdefenseonamipsarchitecture
bdutipo_str Repositorios
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