Desarrollo de encriptado AES en FPGA

The Rijndael cipher, designed by Joan Daemen and Vincent Rijmen and recently selected as the official Advanced Encryption Standard (AES) is well suited for hardware use. This implementation can be carried out through several trade-offs between area and speed. This thesis presents an 8-bit FPGA imple...

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Detalles Bibliográficos
Autor principal: Liberatori, Mónica Cristina
Otros Autores: Bria, Oscar N.
Formato: Tesis Tesis de maestria
Lenguaje:Español
Publicado: 2006
Materias:
Ciencias Informáticas
Redes y Seguridad
Informática
Aplicación informática
Encriptación de datos
Acceso en línea:http://sedici.unlp.edu.ar/handle/10915/4101
https://doi.org/10.35537/10915/4101
http://postgrado.info.unlp.edu.ar/Carreras/Magisters/Redes_de_Datos/Tesis/Liberatori.pdf
Aporte de:
SEDICI (UNLP) de Universidad Nacional de La Plata
id I19-R120-10915-4101
record_format dspace
institution Universidad Nacional de La Plata
institution_str I-19
repository_str R-120
collection SEDICI (UNLP)
language Español
topic Ciencias Informáticas
Redes y Seguridad
Informática
Aplicación informática
Encriptación de datos
spellingShingle Ciencias Informáticas
Redes y Seguridad
Informática
Aplicación informática
Encriptación de datos
Liberatori, Mónica Cristina
Desarrollo de encriptado AES en FPGA
topic_facet Ciencias Informáticas
Redes y Seguridad
Informática
Aplicación informática
Encriptación de datos
description The Rijndael cipher, designed by Joan Daemen and Vincent Rijmen and recently selected as the official Advanced Encryption Standard (AES) is well suited for hardware use. This implementation can be carried out through several trade-offs between area and speed. This thesis presents an 8-bit FPGA implementation of the 128-bit block and 128 bit-key AES cipher. Selected FPGA Family is Altera Flex 10K. The cipher operates at 25 MHz and consumes 470 clock cycles for algorithm encryption, resulting in a throughput of 6.8 Mbps. Synthesis results in the use of 460 logic cells and 4480 memory bits. The VHDL code was simulated using the test vectors provided in the AES submission package. The results are functionally correct. The architecture needs fewer logic cells than other ciphers and uses as few memory blocks as possible. The design goals were area and cost optimisation.
author2 Bria, Oscar N.
author_facet Bria, Oscar N.
Liberatori, Mónica Cristina
format Tesis
Tesis de maestria
author Liberatori, Mónica Cristina
author_sort Liberatori, Mónica Cristina
title Desarrollo de encriptado AES en FPGA
title_short Desarrollo de encriptado AES en FPGA
title_full Desarrollo de encriptado AES en FPGA
title_fullStr Desarrollo de encriptado AES en FPGA
title_full_unstemmed Desarrollo de encriptado AES en FPGA
title_sort desarrollo de encriptado aes en fpga
publishDate 2006
url http://sedici.unlp.edu.ar/handle/10915/4101
https://doi.org/10.35537/10915/4101
http://postgrado.info.unlp.edu.ar/Carreras/Magisters/Redes_de_Datos/Tesis/Liberatori.pdf
work_keys_str_mv AT liberatorimonicacristina desarrollodeencriptadoaesenfpga
bdutipo_str Repositorios
_version_ 1764820473041911809

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