Towards a field configurable non-homogeneous multiprocessors architecture
Standard microprocessors are generally designed to deal efficiently with different types of tasks; their general purpose architecture can lead to misuse of resources, creating a large gap between the computational efficiency of microprocessors and custom silicon. The ever increasing complexity of Fi...
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| Autores principales: | , , |
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| Formato: | Objeto de conferencia |
| Lenguaje: | Inglés |
| Publicado: |
2001
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| Acceso en línea: | http://sedici.unlp.edu.ar/handle/10915/27583 |
| Aporte de: |
| id |
I19-R120-10915-27583 |
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| record_format |
dspace |
| institution |
Universidad Nacional de La Plata |
| institution_str |
I-19 |
| repository_str |
R-120 |
| collection |
SEDICI (UNLP) |
| language |
Inglés |
| topic |
Ingeniería Informática embedded multiprocessing system-on-chip distributed heterogeneous embedded system programmable logic IP cores system-level design |
| spellingShingle |
Ingeniería Informática embedded multiprocessing system-on-chip distributed heterogeneous embedded system programmable logic IP cores system-level design Jaquenod, Guillermo A. Villagarcía Wanza, Horacio A. De Giusti, Marisa Raquel Towards a field configurable non-homogeneous multiprocessors architecture |
| topic_facet |
Ingeniería Informática embedded multiprocessing system-on-chip distributed heterogeneous embedded system programmable logic IP cores system-level design |
| description |
Standard microprocessors are generally designed to deal efficiently with different types of tasks; their general purpose architecture can lead to misuse of resources, creating a large gap between the computational efficiency of microprocessors and custom silicon. The ever increasing complexity of Field Programmable Logic devices is driving the industry to look for innovative System on a Chip solutions; using programmable logic, the whole design can be tuned to the application requirements. In this paper, under the acronym MPOC (Multiprocessors On a Chip) we propose some applicable ideas on multiprocessing embedded configurable architectures, targeting System on a Programmable Chip (SOPC) cost-effective designs. Using heterogeneous medium or low performance soft-core processors instead of a single high performance processor, and some standardized communication schemes to link these multiple processors, the “best” core can be chosen for each subtask using a computational efficiency criteria, and therefore improving silicon usage. System-level design is also considered: models of tasks and links, parameterized soft-core processors, and the use of a standard HDL for system description can lead to automatic generation of the final design. |
| format |
Objeto de conferencia Objeto de conferencia |
| author |
Jaquenod, Guillermo A. Villagarcía Wanza, Horacio A. De Giusti, Marisa Raquel |
| author_facet |
Jaquenod, Guillermo A. Villagarcía Wanza, Horacio A. De Giusti, Marisa Raquel |
| author_sort |
Jaquenod, Guillermo A. |
| title |
Towards a field configurable non-homogeneous multiprocessors architecture |
| title_short |
Towards a field configurable non-homogeneous multiprocessors architecture |
| title_full |
Towards a field configurable non-homogeneous multiprocessors architecture |
| title_fullStr |
Towards a field configurable non-homogeneous multiprocessors architecture |
| title_full_unstemmed |
Towards a field configurable non-homogeneous multiprocessors architecture |
| title_sort |
towards a field configurable non-homogeneous multiprocessors architecture |
| publishDate |
2001 |
| url |
http://sedici.unlp.edu.ar/handle/10915/27583 |
| work_keys_str_mv |
AT jaquenodguillermoa towardsafieldconfigurablenonhomogeneousmultiprocessorsarchitecture AT villagarciawanzahoracioa towardsafieldconfigurablenonhomogeneousmultiprocessorsarchitecture AT degiustimarisaraquel towardsafieldconfigurablenonhomogeneousmultiprocessorsarchitecture |
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Repositorios |
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1764820468197490689 |