Minimum area, low cost fpga implementation of aes
The Rijndael cipher, designed by Joan Daemen and Vincent Rijmen and recently selected as the official Advanced Encryption Standard (AES) is well suited for hardware use. This implementation can be carried out through several trade-offs between area and speed. This paper presents an 8-bit FPGA imple...
Guardado en:
| Autores principales: | Liberatori, Mónica Cristina, Bonadero, Juan Carlos |
|---|---|
| Formato: | Objeto de conferencia |
| Lenguaje: | Inglés |
| Publicado: |
2004
|
| Materias: | |
| Acceso en línea: | http://sedici.unlp.edu.ar/handle/10915/22492 |
| Aporte de: |
Ejemplares similares
-
Daisy Chain Topology on FPGA for naval modernization: implementation and extension with ARP
por: Gallo, Emiliano Sebastián, et al.
Publicado: (2025) -
Metrics for FIR Filters based on distributed arithmetic in FPGA
por: Vázquez, Martín Osvaldo, et al.
Publicado: (2004) -
Post-Quantum Cryptography Using Hyper-Complex Numbers
por: Kamlofsky, Jorge, et al.
Publicado: (2017) -
Open Platform for Digital Design Learning on FPGA-based Systems
por: Heredia, Martín Alejandro, et al.
Publicado: (2020) -
Implementación de MODBUS en FPGA mediante VHDL – Capa de Enlace –
por: Olmedo Sergio, et al.
Publicado: (2011)