Minimum area, low cost fpga implementation of aes
The Rijndael cipher, designed by Joan Daemen and Vincent Rijmen and recently selected as the official Advanced Encryption Standard (AES) is well suited for hardware use. This implementation can be carried out through several trade-offs between area and speed. This paper presents an 8-bit FPGA imple...
| Autores principales: | , |
|---|---|
| Formato: | Objeto de conferencia |
| Lenguaje: | Inglés |
| Publicado: |
2004
|
| Materias: | |
| Acceso en línea: | http://sedici.unlp.edu.ar/handle/10915/22492 |
| Aporte de: | Aportado por :
SEDICI (UNLP) de
Universidad Nacional de La Plata .
|
| id |
I19-R120-10915-22492 |
|---|---|
| record_format |
dspace |
| spelling |
I19-R120-10915-224922018-12-17T20:04:36Z http://sedici.unlp.edu.ar/handle/10915/22492 Minimum area, low cost fpga implementation of aes Liberatori, Mónica Cristina Bonadero, Juan Carlos 2004 2012-10-16T14:17:14Z en Ciencias Informáticas Parallel processing Distributed AES cipher cryptography FPGA VHDL The Rijndael cipher, designed by Joan Daemen and Vincent Rijmen and recently selected as the official Advanced Encryption Standard (AES) is well suited for hardware use. This implementation can be carried out through several trade-offs between area and speed. This paper presents an 8-bit FPGA implementation of the 128-bit block and 128 bit-key AES cipher. Selected FPGA Family is Altera Flex 10K. The cipher operates at 25 MHz and consumes 470 clock cycles for algorithm encryption, resulting in a throughput of 6.8 Mbps. The design target was optimisation of area and cost. Eje: IV - Workshop de procesamiento distribuido y paralelo Red de Universidades con Carreras en Informática (RedUNCI) Objeto de conferencia Objeto de conferencia http://creativecommons.org/licenses/by-nc-sa/2.5/ar/ Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5) application/pdf |
| institution |
Universidad Nacional de La Plata |
| institution_str |
I-19 |
| repository_str |
R-120 |
| collection |
SEDICI (UNLP) |
| language |
Inglés |
| topic |
Ciencias Informáticas Parallel processing Distributed AES cipher cryptography FPGA VHDL |
| spellingShingle |
Ciencias Informáticas Parallel processing Distributed AES cipher cryptography FPGA VHDL Liberatori, Mónica Cristina Bonadero, Juan Carlos Minimum area, low cost fpga implementation of aes |
| topic_facet |
Ciencias Informáticas Parallel processing Distributed AES cipher cryptography FPGA VHDL |
| description |
The Rijndael cipher, designed by Joan Daemen and Vincent Rijmen and recently selected as the official Advanced Encryption Standard (AES) is well suited for hardware use. This implementation can be carried out through several trade-offs between area and speed.
This paper presents an 8-bit FPGA implementation of the 128-bit block and 128 bit-key AES cipher. Selected FPGA Family is Altera Flex 10K. The cipher operates at 25 MHz and consumes 470 clock cycles for algorithm encryption, resulting in a throughput of 6.8 Mbps. The design target was optimisation of area and cost. |
| format |
Objeto de conferencia Objeto de conferencia |
| author |
Liberatori, Mónica Cristina Bonadero, Juan Carlos |
| author_facet |
Liberatori, Mónica Cristina Bonadero, Juan Carlos |
| author_sort |
Liberatori, Mónica Cristina |
| title |
Minimum area, low cost fpga implementation of aes |
| title_short |
Minimum area, low cost fpga implementation of aes |
| title_full |
Minimum area, low cost fpga implementation of aes |
| title_fullStr |
Minimum area, low cost fpga implementation of aes |
| title_full_unstemmed |
Minimum area, low cost fpga implementation of aes |
| title_sort |
minimum area, low cost fpga implementation of aes |
| publishDate |
2004 |
| url |
http://sedici.unlp.edu.ar/handle/10915/22492 |
| work_keys_str_mv |
AT liberatorimonicacristina minimumarealowcostfpgaimplementationofaes AT bonaderojuancarlos minimumarealowcostfpgaimplementationofaes |
| _version_ |
1734119904815087616 |