FPGA-Based Digital filters using Bit-Serial arithmetic

This paper presents an efficient method for implementation of digital filters targeted FPGA architectures. The traditional approach is based on application of general purpose multipliers. However, multipliers implemented in FPGA architectures do not allow to construct economic Digital Filters. For thi...

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Detalles Bibliográficos
Autores principales: Arroyuelo, Mónica, Arroyuelo, Jorge, Grosso, Alejandro
Formato: Objeto de conferencia
Lenguaje:Español
Publicado: 2007
Materias:
Ciencias Informáticas
Informática
Information filtering
Filtering
digital filter
FIR-Filter
IIR-Filter
lookup tables
Acceso en línea:http://sedici.unlp.edu.ar/handle/10915/21693
Aporte de:
SEDICI (UNLP) de Universidad Nacional de La Plata
id I19-R120-10915-21693
record_format dspace
institution Universidad Nacional de La Plata
institution_str I-19
repository_str R-120
collection SEDICI (UNLP)
language Español
topic Ciencias Informáticas
Informática
Information filtering
Filtering
digital filter
FIR-Filter
IIR-Filter
lookup tables
spellingShingle Ciencias Informáticas
Informática
Information filtering
Filtering
digital filter
FIR-Filter
IIR-Filter
lookup tables
Arroyuelo, Mónica
Arroyuelo, Jorge
Grosso, Alejandro
FPGA-Based Digital filters using Bit-Serial arithmetic
topic_facet Ciencias Informáticas
Informática
Information filtering
Filtering
digital filter
FIR-Filter
IIR-Filter
lookup tables
description This paper presents an efficient method for implementation of digital filters targeted FPGA architectures. The traditional approach is based on application of general purpose multipliers. However, multipliers implemented in FPGA architectures do not allow to construct economic Digital Filters. For this reason, multipliers are replaced by Lookup Tables and Adder-Substractor, which use Bit-Serial Arithmetic. Lookup Tables can be of considerable size in high order filters, thus interconnection techniques will be used to construct high order filters from a set of low order filters. The paper presents several examples confirming that these techniques allow a reduction in logic cells utilization of filters implementation based on Bit-Serial Arithmetic concept.
format Objeto de conferencia
Objeto de conferencia
author Arroyuelo, Mónica
Arroyuelo, Jorge
Grosso, Alejandro
author_facet Arroyuelo, Mónica
Arroyuelo, Jorge
Grosso, Alejandro
author_sort Arroyuelo, Mónica
title FPGA-Based Digital filters using Bit-Serial arithmetic
title_short FPGA-Based Digital filters using Bit-Serial arithmetic
title_full FPGA-Based Digital filters using Bit-Serial arithmetic
title_fullStr FPGA-Based Digital filters using Bit-Serial arithmetic
title_full_unstemmed FPGA-Based Digital filters using Bit-Serial arithmetic
title_sort fpga-based digital filters using bit-serial arithmetic
publishDate 2007
url http://sedici.unlp.edu.ar/handle/10915/21693
work_keys_str_mv AT arroyuelomonica fpgabaseddigitalfiltersusingbitserialarithmetic
AT arroyuelojorge fpgabaseddigitalfiltersusingbitserialarithmetic
AT grossoalejandro fpgabaseddigitalfiltersusingbitserialarithmetic
bdutipo_str Repositorios
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