Improving the throughput of an mt processor
Multithreading (MT), by simultaneously using both the thread-level parallelism and the instruction-level parallelism of a workload, exploits the available resources more efficiently than single-thread processors allowing a better throughput, i.e there are more instructions per cycle (IPC), over the...
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| Autores principales: | , , |
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| Formato: | Objeto de conferencia |
| Lenguaje: | Inglés |
| Publicado: |
2001
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| Materias: | |
| Acceso en línea: | http://sedici.unlp.edu.ar/handle/10915/21607 |
| Aporte de: |
| Sumario: | Multithreading (MT), by simultaneously using both the thread-level parallelism and the instruction-level parallelism of a workload, exploits the available resources more efficiently than single-thread processors allowing a better throughput, i.e there are more instructions per cycle (IPC), over the single thread approach. An MT approach is a chip multiprocessor (CMP), which is a static one that could exploit a moderate amount of the ILP on a fixed number of threads. The other one, simultaneous multithreading (SMT) [2], uses dynamic mechanisms and policies to exploit the available ILP of a varying number of threads. SMT using both TLP and ILP interchangeably will provide larger IPC rates than CMP. However, due to its complex and tightly coupled microarchitecture, SMT increases the pressure on cycle time. |
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