Improving the throughput of an mt processor

Multithreading (MT), by simultaneously using both the thread-level parallelism and the instruction-level parallelism of a workload, exploits the available resources more efficiently than single-thread processors allowing a better throughput, i.e there are more instructions per cycle (IPC), over the...

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Detalles Bibliográficos
Autores principales: García, Rafael B., Ardenghi, Jorge Raúl, Echaiz, Javier
Formato: Objeto de conferencia
Lenguaje:Inglés
Publicado: 2001
Materias:
Ciencias Informáticas
arquitectura
Real time
Distributed Systems
Improving the throughput
mt processor
Acceso en línea:http://sedici.unlp.edu.ar/handle/10915/21607
Aporte de:
SEDICI (UNLP) de Universidad Nacional de La Plata
id I19-R120-10915-21607
record_format dspace
institution Universidad Nacional de La Plata
institution_str I-19
repository_str R-120
collection SEDICI (UNLP)
language Inglés
topic Ciencias Informáticas
arquitectura
Real time
Distributed Systems
Improving the throughput
mt processor
spellingShingle Ciencias Informáticas
arquitectura
Real time
Distributed Systems
Improving the throughput
mt processor
García, Rafael B.
Ardenghi, Jorge Raúl
Echaiz, Javier
Improving the throughput of an mt processor
topic_facet Ciencias Informáticas
arquitectura
Real time
Distributed Systems
Improving the throughput
mt processor
description Multithreading (MT), by simultaneously using both the thread-level parallelism and the instruction-level parallelism of a workload, exploits the available resources more efficiently than single-thread processors allowing a better throughput, i.e there are more instructions per cycle (IPC), over the single thread approach. An MT approach is a chip multiprocessor (CMP), which is a static one that could exploit a moderate amount of the ILP on a fixed number of threads. The other one, simultaneous multithreading (SMT) [2], uses dynamic mechanisms and policies to exploit the available ILP of a varying number of threads. SMT using both TLP and ILP interchangeably will provide larger IPC rates than CMP. However, due to its complex and tightly coupled microarchitecture, SMT increases the pressure on cycle time.
format Objeto de conferencia
Objeto de conferencia
author García, Rafael B.
Ardenghi, Jorge Raúl
Echaiz, Javier
author_facet García, Rafael B.
Ardenghi, Jorge Raúl
Echaiz, Javier
author_sort García, Rafael B.
title Improving the throughput of an mt processor
title_short Improving the throughput of an mt processor
title_full Improving the throughput of an mt processor
title_fullStr Improving the throughput of an mt processor
title_full_unstemmed Improving the throughput of an mt processor
title_sort improving the throughput of an mt processor
publishDate 2001
url http://sedici.unlp.edu.ar/handle/10915/21607
work_keys_str_mv AT garciarafaelb improvingthethroughputofanmtprocessor
AT ardenghijorgeraul improvingthethroughputofanmtprocessor
AT echaizjavier improvingthethroughputofanmtprocessor
bdutipo_str Repositorios
_version_ 1764820464739287043

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