A system to detect timing problems in digital circuits
Nowadays, the digital circuit production is carried out specifying the circuit functionality using a hardware description language. Then, this specification is synthesized down to a structural netlist suitable for use by the target technologys place-and-route applications. Many synthesis tools make...
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| Autores principales: | , , , , , , , , |
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| Formato: | Objeto de conferencia |
| Lenguaje: | Español |
| Publicado: |
2010
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| Materias: | |
| Acceso en línea: | http://sedici.unlp.edu.ar/handle/10915/19296 |
| Aporte de: |
| Sumario: | Nowadays, the digital circuit production is carried out specifying the circuit functionality using a hardware description language. Then, this specification is synthesized down to a structural netlist suitable for use by the target technologys place-and-route applications. Many synthesis tools make this task introducing some unnecessary gates and wires in the final circuit. As a consequence, it can appear a circuit containing one or more paths that do not influence the circuit output. This kind of non-relevant paths is known as False Path.
The problem with false paths is that if they are not considered, the circuit delay may be overestimated during design analysis and optimization. For this reason, the digital circuit industry is looking for effective methods and tools to overcome the mentioned drawbacks. This paper presents a system to detect False Paths based on the analysis of the circuit intermediate specification. The tool analyzes the specification using compilation techniques and then applies some special purpose algorithms for detecting false paths. Furthermore, it shows the gates and wires that are not necessary for the circuit final version. |
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