Real-time SSVEP measurements through Lock-in detection in FPGA-based platform

In this work, a method for measuring steady-state visually evoked potentials using the Lock-In technique is presented. The proposed method in- volves acquiring the electroencephalography signal through channel averaging from an ADS1299 sigma-delta converter, without the need for additional hardware...

Descripción completa

Detalles Bibliográficos
Autores principales: Oliva, Matías Javier, Guerrero, Federico Nicolás, García, Pablo Andrés, Spinelli, Enrique Mario
Formato: Objeto de conferencia
Lenguaje:Inglés
Publicado: 2023
Materias:
Ingeniería
SSVEP
FPGA
EEG
Lock-in
Acceso en línea:http://sedici.unlp.edu.ar/handle/10915/160849
Aporte de:
SEDICI (UNLP) de Universidad Nacional de La Plata
id I19-R120-10915-160849
record_format dspace
spelling I19-R120-10915-1608492023-11-30T04:07:21Z http://sedici.unlp.edu.ar/handle/10915/160849 Real-time SSVEP measurements through Lock-in detection in FPGA-based platform Oliva, Matías Javier Guerrero, Federico Nicolás García, Pablo Andrés Spinelli, Enrique Mario 2023-10 2023 2023-11-29T13:35:10Z en Ingeniería SSVEP FPGA EEG Lock-in In this work, a method for measuring steady-state visually evoked potentials using the Lock-In technique is presented. The proposed method in- volves acquiring the electroencephalography signal through channel averaging from an ADS1299 sigma-delta converter, without the need for additional hardware to accommodate the signal and processing in real-time using an Intel MAX10 FPGA, while visual stimuli synchronized with the sampling and pro- cessing are generated. The result is a robust platform that allows determining a user's attention focus on visual stimuli flickering at 14.70, 16.67, and 19.23 Hz. The initial experimental tests of the system with three subjects validated the platform, obtaining an average signal-to-noise ratio of 3.2 in the detection, with a maximum of 6.2 in the case of an experienced SSVEP user. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales Objeto de conferencia Objeto de conferencia http://creativecommons.org/licenses/by-nc-nd/4.0/ Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0) application/pdf
institution Universidad Nacional de La Plata
institution_str I-19
repository_str R-120
collection SEDICI (UNLP)
language Inglés
topic Ingeniería
SSVEP
FPGA
EEG
Lock-in
spellingShingle Ingeniería
SSVEP
FPGA
EEG
Lock-in
Oliva, Matías Javier
Guerrero, Federico Nicolás
García, Pablo Andrés
Spinelli, Enrique Mario
Real-time SSVEP measurements through Lock-in detection in FPGA-based platform
topic_facet Ingeniería
SSVEP
FPGA
EEG
Lock-in
description In this work, a method for measuring steady-state visually evoked potentials using the Lock-In technique is presented. The proposed method in- volves acquiring the electroencephalography signal through channel averaging from an ADS1299 sigma-delta converter, without the need for additional hardware to accommodate the signal and processing in real-time using an Intel MAX10 FPGA, while visual stimuli synchronized with the sampling and pro- cessing are generated. The result is a robust platform that allows determining a user's attention focus on visual stimuli flickering at 14.70, 16.67, and 19.23 Hz. The initial experimental tests of the system with three subjects validated the platform, obtaining an average signal-to-noise ratio of 3.2 in the detection, with a maximum of 6.2 in the case of an experienced SSVEP user.
format Objeto de conferencia
Objeto de conferencia
author Oliva, Matías Javier
Guerrero, Federico Nicolás
García, Pablo Andrés
Spinelli, Enrique Mario
author_facet Oliva, Matías Javier
Guerrero, Federico Nicolás
García, Pablo Andrés
Spinelli, Enrique Mario
author_sort Oliva, Matías Javier
title Real-time SSVEP measurements through Lock-in detection in FPGA-based platform
title_short Real-time SSVEP measurements through Lock-in detection in FPGA-based platform
title_full Real-time SSVEP measurements through Lock-in detection in FPGA-based platform
title_fullStr Real-time SSVEP measurements through Lock-in detection in FPGA-based platform
title_full_unstemmed Real-time SSVEP measurements through Lock-in detection in FPGA-based platform
title_sort real-time ssvep measurements through lock-in detection in fpga-based platform
publishDate 2023
url http://sedici.unlp.edu.ar/handle/10915/160849
work_keys_str_mv AT olivamatiasjavier realtimessvepmeasurementsthroughlockindetectioninfpgabasedplatform
AT guerrerofedericonicolas realtimessvepmeasurementsthroughlockindetectioninfpgabasedplatform
AT garciapabloandres realtimessvepmeasurementsthroughlockindetectioninfpgabasedplatform
AT spinellienriquemario realtimessvepmeasurementsthroughlockindetectioninfpgabasedplatform
_version_ 1807221983370280960

Ejemplares similares