A 6-bit 2GS/s CMOS Time-Interleaved ADC for Analysis of Mixed-Signal Calibration Techniques
A 6-bit 2-GS/s time interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) is designed and fabricated in a 0.13 μm CMOS process. The architecture uses 8 time-interleaved track-and-hold amplifiers (THA), and 16 SARADC’s. Thechipincludes (i) a programmable delay cel...
Guardado en:
| Autores principales: | Reyes, Benjamín, Tealdi, Lucas, Paulina, German, Labat, Emanuel, Sánchez, Raúl, Mandolesi, Pablo, Hueda, Mario |
|---|---|
| Formato: | conferenceObject |
| Lenguaje: | Inglés |
| Publicado: |
2022
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| Materias: | |
| Acceso en línea: | http://hdl.handle.net/11086/22937 |
| Aporte de: |
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