Multi-match Packet Classification on Memory-Logic Trade-off FPGA-based Architecture

Packet processing is becoming much more challenging as networks evolve towards a multi-service platform. In particular, packet classification demands smaller processing times as data rates increase. To successfully meet this requirement, hardware-based classification architectures have become an are...

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Autores principales: Zerbini, Carlos A., Finochietto, Jorge M.
Formato: conferenceObject
Lenguaje:Inglés
Publicado: 2022
Materias:
Pipeline processing
Field-programmable
Hardware-based
Classification architectures
Acceso en línea:http://hdl.handle.net/11086/28727
Aporte de:
Repositorio Digital Universitario (UNC) de Universidad Nacional de Córdoba
id I10-R141-11086-28727
record_format dspace
institution Universidad Nacional de Córdoba
institution_str I-10
repository_str R-141
collection Repositorio Digital Universitario (UNC)
language Inglés
topic Pipeline processing
Field-programmable
Hardware-based
Classification architectures
spellingShingle Pipeline processing
Field-programmable
Hardware-based
Classification architectures
Zerbini, Carlos A.
Finochietto, Jorge M.
Multi-match Packet Classification on Memory-Logic Trade-off FPGA-based Architecture
topic_facet Pipeline processing
Field-programmable
Hardware-based
Classification architectures
description Packet processing is becoming much more challenging as networks evolve towards a multi-service platform. In particular, packet classification demands smaller processing times as data rates increase. To successfully meet this requirement, hardware-based classification architectures have become an area of extensive research. Even if Field Programmable Logic Arrays (FPGAs) have emerged as an interesting technology for implementing these architectures, existing proposals either exploit maximal concurrency with unbounded resource consumption, or base the architecture on distributed RAM memory-based schemes which strongly undervalues FPGA capabilities. Moreover, most of these proposals target best-match classification and are not suited for high-speed updates of classification rulesets. In this paper, we propose a new approach which exploits rich logic resources available in modern FPGAs while reducing memory consumption. Our architecture is conceived for multi-match classification, and its mapping methodology is naturally suited for high-speed, simple updating of the classification ruleset. Analytical evaluation and implementation results of our architecture are promising, demonstrating that it is suitable for line speed processing with balanced resource consumption. With additional optimizations, our proposal has the potential to be integrated into network processing architectures demanding all aforementioned features.
format conferenceObject
author Zerbini, Carlos A.
Finochietto, Jorge M.
author_facet Zerbini, Carlos A.
Finochietto, Jorge M.
author_sort Zerbini, Carlos A.
title Multi-match Packet Classification on Memory-Logic Trade-off FPGA-based Architecture
title_short Multi-match Packet Classification on Memory-Logic Trade-off FPGA-based Architecture
title_full Multi-match Packet Classification on Memory-Logic Trade-off FPGA-based Architecture
title_fullStr Multi-match Packet Classification on Memory-Logic Trade-off FPGA-based Architecture
title_full_unstemmed Multi-match Packet Classification on Memory-Logic Trade-off FPGA-based Architecture
title_sort multi-match packet classification on memory-logic trade-off fpga-based architecture
publishDate 2022
url http://hdl.handle.net/11086/28727
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bdutipo_str Repositorios
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