A scheduler synthesis methodology for joint SW/HW design exploration of SoC
The introduction of high-performance applications such as multimedia applications into SoCs led the manufacturers to provide embedded SoCs able to offer an important computing power which makes it possible to answer the increasing requirements of future evolutions of these applications. One of the a...
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2010
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| Acceso en línea: | Registro en Scopus DOI Handle Registro en la Biblioteca Digital |
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| LEADER | 09774caa a22009257a 4500 | ||
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| 001 | PAPER-22883 | ||
| 003 | AR-BaUEN | ||
| 005 | 20230518205429.0 | ||
| 008 | 190411s2010 xx ||||fo|||| 00| 0 eng|d | ||
| 024 | 7 | |2 scopus |a 2-s2.0-77956912418 | |
| 040 | |a Scopus |b spa |c AR-BaUEN |d AR-BaUEN | ||
| 030 | |a DAESF | ||
| 100 | 1 | |a Assayad, I. | |
| 245 | 1 | 2 | |a A scheduler synthesis methodology for joint SW/HW design exploration of SoC |
| 260 | |c 2010 | ||
| 270 | 1 | 0 | |m Assayad, I.; ENSEM, University of Hassan II Ain Chock, Oasis Casablanca, Morocco; email: i.assayad@ensem.ac.ma |
| 506 | |2 openaire |e Política editorial | ||
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| 504 | |a Assayad, I., Yovine, S., System platform simulation model applied to multiprocessor video encoding (2006) IEEE Symposium on Industrial Embedded Systems | ||
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| 504 | |a Assayad, I., Yovine, S., Compositional constraints generation for concurrent real time loops with interdependent iterations (2005) I2CS'05. LNCS, , Springer, Berlin | ||
| 504 | |a Assayad, I., Yovine, S., Modelling and exploration environment for application specific multiprocessor systems (2007) HASE '07. IEEE CS, pp. 433-434. , Washington | ||
| 504 | |a Assayad, I., Gerner, P., Yovine, S., Bertin, V., Modelling, analysis and implementation of an on-line video encoder (2005) DFMA'05. IEEE Computer Society, , Washington | ||
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| 520 | 3 | |a The introduction of high-performance applications such as multimedia applications into SoCs led the manufacturers to provide embedded SoCs able to offer an important computing power which makes it possible to answer the increasing requirements of future evolutions of these applications. One of the adopted solutions is the use of multiprocessor SoCs. In this paper, we present a joint SW/HW design exploration methodology for multiprocessor SoCs. The system model relies on transaction-level component-based models for modeling parallel software and multiprocessor hardware. Our proposal comprises two original points. First, we propose a composable software-level scheduler constraints synthesis technique. Second, we present a combined software-level and exploratory hardwarelevel schedulers. The methodology has the advantage of combining real-time requirements of software with effective exploitation of multiprocessor hardware. We describe and apply the methodology to synthesize a scheduler of a slice-based MPEG-4 video encoder on the multiprocessor Cake SoCs. © Springer Science+Business Media, LLC 2010. |l eng | |
| 593 | |a ENSEM, University of Hassan II Ain Chock, Oasis Casablanca, Morocco | ||
| 593 | |a Departamento de Computacion, Universidad de Buenos Aires, Researcher at CONICET, Buenos Aires, Argentina | ||
| 690 | 1 | 0 | |a EXPLORATION |
| 690 | 1 | 0 | |a MULTIPROCESSOR SYSTEM-ON-CHIPS (SOCS) |
| 690 | 1 | 0 | |a REAL-TIME REQUIREMENTS |
| 690 | 1 | 0 | |a SCHEDULING |
| 690 | 1 | 0 | |a SW/HW DESIGN |
| 690 | 1 | 0 | |a COMPONENT-BASED MODELS |
| 690 | 1 | 0 | |a COMPUTING POWER |
| 690 | 1 | 0 | |a EXPLORATION |
| 690 | 1 | 0 | |a HIGH PERFORMANCE APPLICATIONS |
| 690 | 1 | 0 | |a MPEG-4 VIDEO ENCODERS |
| 690 | 1 | 0 | |a MULTI-PROCESSOR HARDWARE |
| 690 | 1 | 0 | |a MULTIMEDIA APPLICATIONS |
| 690 | 1 | 0 | |a MULTIPROCESSOR SYSTEM ON CHIPS |
| 690 | 1 | 0 | |a PARALLEL SOFTWARE |
| 690 | 1 | 0 | |a REAL TIME REQUIREMENT |
| 690 | 1 | 0 | |a SW/HW DESIGN |
| 690 | 1 | 0 | |a SYNTHESIS METHODOLOGY |
| 690 | 1 | 0 | |a SYNTHESIS TECHNIQUES |
| 690 | 1 | 0 | |a SYSTEM MODELS |
| 690 | 1 | 0 | |a DESIGN |
| 690 | 1 | 0 | |a MOTION PICTURE EXPERTS GROUP STANDARDS |
| 690 | 1 | 0 | |a SCHEDULING |
| 690 | 1 | 0 | |a TIMING JITTER |
| 690 | 1 | 0 | |a MULTIPROCESSING SYSTEMS |
| 700 | 1 | |a Yovine, S. | |
| 773 | 0 | |d 2010 |g v. 14 |h pp. 75-103 |k n. 2 |p Des Autom Embedded Syst |x 09295585 |t Design Automation for Embedded Systems | |
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| 856 | 4 | 0 | |u https://doi.org/10.1007/s10617-010-9051-5 |y DOI |
| 856 | 4 | 0 | |u https://hdl.handle.net/20.500.12110/paper_09295585_v14_n2_p75_Assayad |y Handle |
| 856 | 4 | 0 | |u https://bibliotecadigital.exactas.uba.ar/collection/paper/document/paper_09295585_v14_n2_p75_Assayad |y Registro en la Biblioteca Digital |
| 961 | |a paper_09295585_v14_n2_p75_Assayad |b paper |c PE | ||
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