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240321s2015 usa|||fo 00| 0 engdd |
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|a 9781315216072
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|a https://doi.org/10.1201/9781315216072
|2 DOI
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|a AR-OvUNE
|c AR-OvUNE
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|a 621.38.037.37
|b KUN
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|a Kundu, Santanu
|9 31760
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|a Network-on-Chip
|h [recurso electrónico] :
|b the next generation of system-on-chip integration /
|c Santanu Kundu, Santanu Chattopadhyay
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|a Boca Raton, FL :
|b CRC Press,
|c c2015.
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|a recurso en línea (ca. 388 p.) :
|b fig. byn.
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|a Texto (visual)
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|a electrónico
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|a recurso en línea
|2 RDA carrier types
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|a Permite bajar el texto completo (5.48 MB) o leerlo en línea
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|a 1. Introduction -- 2. Interconnection networks in network-on-chip -- 3. Architecture design of network-on-chip -- 4. Evaluation of network-on-chip architectures -- 5. Application mapping on network-on-chip -- 6. Low-power techniques for network-on-chip -- 7. Signal integrity and reliability of network-on-chip -- 8. Testing of network-on-chip architectures -- 9. Application-specific network-on-chip synthesis -- 10. Reconfigurable network-on-chip design -- 11. Three-dimensional integration of network-on-chip -- 12. Conclusions and future trends
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|a Creative Commons, CC BY-NC
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|a Circuitos integrados digitales
|9 31308
|2 embne
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|a SYSTEM-ON-CHIP
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|a SISTEMA EN CHIP
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|a NETWORK-ON-CHIP
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|a DESARROLLO DE REDES DENTRO DEL CHIP
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|a SoC
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|a NoC
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700 |
1 |
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|a Chattopadhyay, Santanu
|9 31759
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4 |
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|u https://www.taylorfrancis.com/books/oa-mono/10.1201/9781315216072/network-chip-santanu-kundu-santanu-chattopadhyay
|y Acceso al texto completo
|z (última consulta: 21/03/2024)
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856 |
4 |
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|u https://books.google.com.ar/books?id=pWVYBQAAQBAJ&lpg=PP1&hl=es&pg=PR5#v=onepage&q&f=false
|y Acceso alternativo al texto completo
|z (última consulta: 21/03/2024)
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|2 udc
|h 621.38.037.37
|c LIB
|6 6213803737
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|c 13081
|d 13081
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