Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects.  The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge re...

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Detalles Bibliográficos
Autor principal: Noia, Brandon
Otros Autores: Chakrabarty, Krishnendu
Formato: Libro electrónico
Lenguaje:Inglés
Publicado: Cham : Springer International Publishing : Imprint: Springer, 2014.
Materias:
Engineering.
Microprocessors.
Semiconductors.
Electronic circuits.
Circuits and Systems.
Processor Architectures.
Acceso en línea:http://dx.doi.org/10.1007/978-3-319-02378-6
Aporte de:Registro referencial: Solicitar el recurso aquí
Bibliotecas (ING-UNLP) de Universidad Nacional de La Plata
Tabla de Contenidos:
  • Introduction
  • Wafer Stacking and 3D Memory Test
  • Built-in Self-Test for TSVs
  • Pre-Bond TSV Test Through TSV Probing
  • Pre-Bond TSV Test Through TSV Probing
  • Overcoming the Timing Overhead of Test Architectures on Inter-Die Critical Paths
  • Post-Bond Test Wrappers and Emerging Test Standards
  • Test-Architecture Optimization and Test Scheduling
  • Conclusions.

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