Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge re...
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| Autor principal: | |
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| Otros Autores: | |
| Formato: | Libro electrónico |
| Lenguaje: | Inglés |
| Publicado: |
Cham :
Springer International Publishing : Imprint: Springer,
2014.
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| Materias: | |
| Acceso en línea: | http://dx.doi.org/10.1007/978-3-319-02378-6 |
| Aporte de: | Registro referencial: Solicitar el recurso aquí |
| LEADER | 02931Cam#a22004335i#4500 | ||
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| 020 | |a 9783319023786 | ||
| 024 | 7 | |a 10.1007/978-3-319-02378-6 |2 doi | |
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| 100 | 1 | |a Noia, Brandon. |9 260659 | |
| 245 | 1 | 0 | |a Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs |h [libro electrónico] / |c by Brandon Noia, Krishnendu Chakrabarty. |
| 260 | 1 | |a Cham : |b Springer International Publishing : |b Imprint: Springer, |c 2014. | |
| 300 | |a xviii, 245 p. : |b il. | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
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| 505 | 0 | |a Introduction -- Wafer Stacking and 3D Memory Test -- Built-in Self-Test for TSVs -- Pre-Bond TSV Test Through TSV Probing -- Pre-Bond TSV Test Through TSV Probing -- Overcoming the Timing Overhead of Test Architectures on Inter-Die Critical Paths -- Post-Bond Test Wrappers and Emerging Test Standards -- Test-Architecture Optimization and Test Scheduling -- Conclusions. | |
| 520 | |a This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.  â_¢Â Provides a comprehensive guide to the challenges and solutions for the testing of TSV-based 3D stacked ICs; â_¢Â Includes in-depth explanation of key test and design-for-test technologies, emerging standards, and test- architecture and test-schedule optimizations; â_¢Â Encompasses all aspects of test as related to 3D ICs, including pre-bond and post-bond test as well as the test optimization and scheduling necessary to ensure that 3D testing remains cost-effective.  . | ||
| 650 | 0 | |a Engineering. |9 259622 | |
| 650 | 0 | |a Microprocessors. |9 259640 | |
| 650 | 0 | |a Semiconductors. |9 259967 | |
| 650 | 0 | |a Electronic circuits. |9 259798 | |
| 650 | 2 | 4 | |a Circuits and Systems. |9 259651 |
| 650 | 2 | 4 | |a Processor Architectures. |9 259645 |
| 700 | 1 | |a Chakrabarty, Krishnendu. |9 260660 | |
| 776 | 0 | 8 | |i Printed edition: |z 9783319023779 |
| 856 | 4 | 0 | |u http://dx.doi.org/10.1007/978-3-319-02378-6 |
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