Embedded Memory Design for Multi-Core and Systems on Chip

This book describes the various tradeoffs systems designers face when designing embedded memory.  Readers designing multi-core systems and systems on chip will benefit from the discussion of different topics from memory architecture, array organization, circuit design techniques and design for test...

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Detalles Bibliográficos
Autor principal: Mohammad, Baker
Formato: Libro electrónico
Lenguaje:Inglés
Publicado: New York, NY : Springer New York : Imprint: Springer, 2014.
Colección:Analog Circuits and Signal Processing, 116
Materias:
Acceso en línea:http://dx.doi.org/10.1007/978-1-4614-8881-1
Aporte de:Registro referencial: Solicitar el recurso aquí
LEADER 02957Cam#a22004575i#4500
001 INGC-EBK-000125
003 AR-LpUFI
005 20220927105642.0
007 cr nn 008mamaa
008 131022s2014 xxu| s |||| 0|eng d
020 |a 9781461488811 
024 7 |a 10.1007/978-1-4614-8881-1  |2 doi 
050 4 |a TK7888.4 
072 7 |a TJFC  |2 bicssc 
072 7 |a TEC008010  |2 bisacsh 
100 1 |a Mohammad, Baker.  |9 260181 
245 1 0 |a Embedded Memory Design for Multi-Core and Systems on Chip   |h [libro electrónico] /   |c by Baker Mohammad. 
260 1 |a New York, NY :  |b Springer New York :  |b Imprint: Springer,  |c 2014. 
300 |a xiii, 95 p. :   |b il. 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b c  |2 rdamedia 
338 |a online resource  |b cr  |2 rdacarrier 
347 |a text file  |b PDF  |2 rda 
490 1 |a Analog Circuits and Signal Processing,  |x 1872-082X ;  |v 116 
505 0 |a Introduction -- Cache Architecture and Main Blocks -- Embedded Memory Hierarchy -- SRAM Memory Operation and Yield -- Low Power and High Yield SRAM Memory -- Leakage Reduction -- Embedded Memory Verification -- Embedded Memory Design Validation and Design For Test -- Emerging Memory Technology Opportunities and Challenges. 
520 |a This book describes the various tradeoffs systems designers face when designing embedded memory.  Readers designing multi-core systems and systems on chip will benefit from the discussion of different topics from memory architecture, array organization, circuit design techniques and design for test.  The presentation enables a multi-disciplinary approach to chip design, which bridges the gap between the architecture level and circuit level, in order to address yield, reliability and power-related issues for embedded memory.  ·         Provides a comprehensive overview of embedded memory design and associated challenges and choices; ·         Explains tradeoffs and dependencies across different disciplines involved with multi-core and system on chip memory design; ·         Includes detailed discussion of memory hierarchy and its impact on energy and performance; ·         Uses real product examples to demonstrate embedded memory design flow from architecture, to circuit design, design for test and yield analysis. 
650 0 |a Engineering.  |9 259622 
650 0 |a Microprocessors.  |9 259640 
650 0 |a Electronics.  |9 259648 
650 0 |a Microelectronics.  |9 259649 
650 0 |a Electronic circuits.  |9 259798 
650 2 4 |a Circuits and Systems.  |9 259651 
650 2 4 |a Instrumentation.  |9 259652 
650 2 4 |a Processor Architectures.  |9 259645 
776 0 8 |i Printed edition:  |z 9781461488804 
856 4 0 |u http://dx.doi.org/10.1007/978-1-4614-8881-1 
912 |a ZDB-2-ENG 
929 |a COM 
942 |c EBK  |6 _ 
950 |a Engineering (Springer-11647) 
999 |a SKV  |c 27553  |d 27553