Synthesis of arithmetic circuits : FPGA, ASIC and embedded systems /
Guardado en:
| Autor principal: | |
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| Otros Autores: | , |
| Formato: | Libro |
| Lenguaje: | Inglés |
| Publicado: |
Hoboken, N.J. :
John Wiley,
2005.
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| Materias: | |
| Acceso en línea: | Table of contents Contributor biographical information Publisher description |
| Aporte de: | Registro referencial: Solicitar el recurso aquí |
| LEADER | 01275nam a2200349 4500 | ||
|---|---|---|---|
| 001 | 032870 | ||
| 003 | arbauncb | ||
| 008 | 050204s2005 nju g 000 0 eng | ||
| 005 | 20171018141405.0 | ||
| 040 | |a AR-BaUNCB |c AR-BaUNCB | ||
| 040 | |a DLC |c DLC |d FUN | ||
| 245 | 1 | 0 | |a Synthesis of arithmetic circuits : |b FPGA, ASIC and embedded systems / |c Jean-Pierre Deschamps, Gery Jean Antoine Bioul, Gustavo D. Sutter. |
| 260 | |a Hoboken, N.J. : |b John Wiley, |c 2005. | ||
| 263 | |a 0509 | ||
| 300 | |a 556 p. ; |c 23 cm. | ||
| 020 | |a 0471687839 (cloth) | ||
| 100 | 1 | |a Deschamps, Jean-Pierre, |d 1945- | |
| 700 | 1 | |a Bioul, Gery Jean Antoine. | |
| 700 | 1 | |a Sutter, Gustavo D. | |
| 082 | 0 | 0 | |a 621.395 |
| 650 | 0 | |a Computación |2 mpirdes | |
| 653 | |a Arquitectura-computación | ||
| 653 | |a ALU | ||
| 653 | |a Unidad aritmética lógica | ||
| 653 | |a FPGA | ||
| 653 | |a Field-programmable gate arrays | ||
| 010 | |a \\2005003237 | ||
| 050 | 0 | 0 | |a TK7895.A65 |b D47 2005 |
| 856 | 4 | 1 | |3 Table of contents |u http://www.loc.gov/catdir/toc/ecip057/2005003237.html |
| 856 | 4 | 2 | |3 Contributor biographical information |u http://www.loc.gov/catdir/enhancements/fy0621/2005003237-b.html |
| 856 | 4 | 2 | |3 Publisher description |u http://www.loc.gov/catdir/enhancements/fy0621/2005003237-d.html |
| 999 | |c 32761 |d 32761 | ||