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20200306155400.0 |
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120301t2011 |||a 00 0 eng d |
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|a AR-SjUIP
|c AR-SjUIP
|
900 |
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|a Proyecto Huarpe
|b 6699
|c 6699
|d Proyecto Huarpe
|
020 |
|
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|a 9780470688472
|
245 |
1 |
0 |
|a VHDL for logic synthesis /
|c Andrew Rushton.
|
250 |
|
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|a 3rd ed.
|
260 |
|
|
|a U.K. :
|b Wiley,
|c 2011.
|
080 |
|
|
|a 004.2/.4
|2 UNE 50001:2000
|
650 |
|
7 |
|a LENGUAJE DE PROGRAMACION
|9 161574
|
650 |
|
7 |
|a MULTIPROCESO
|9 210701
|
650 |
|
7 |
|a LOGICA MATEMATICA
|9 213320
|
650 |
|
7 |
|a PROCESO DE DATOS
|9 165685
|
650 |
|
7 |
|a OPERADORES LOGICOS
|9 191087
|
650 |
|
7 |
|a BIBLIOTECAS DE PROGRAMAS
|9 208956
|
650 |
|
7 |
|a SECUENCIA LOGICA
|9 213164
|
100 |
1 |
|
|a Rushton, Andrew
|9 213321
|
300 |
|
|
|a xvi, 466 p. :
|b il. ; diagrs. ;
|c 25 cm.
|
504 |
|
|
|
942 |
|
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|2 udc
|c LIB
|
999 |
|
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|c 154155
|d 154155
|