|
|
|
|
| LEADER |
01012nam a22003015a 4500 |
| 001 |
1039 |
| 003 |
AR-SjUIP |
| 005 |
20200306155237.0 |
| 008 |
111108t2006 |||a 00 0 eng d |
| 040 |
|
|
|a AR-SjUIP
|c AR-SjUIP
|
| 900 |
|
|
|a Proyecto Huarpe
|b 6699
|c 6699
|d Proyecto Huarpe
|
| 020 |
|
|
|a 9780471720928
|
| 245 |
1 |
0 |
|a RTL hardware design using VHDL :
|b coding for efficiency, portability, and scalability /
|c Pong P. Chu.
|
| 260 |
|
|
|a New Jersey :
|b Wiley & Sons,
|c 2006.
|
| 500 |
|
|
|a Bibliografía e índice al final de la obra.
|
| 080 |
|
|
|a 004.21.4
|2 UNE 50001:2000
|
| 650 |
|
7 |
|a MULTIPROCESO
|9 210701
|
| 650 |
|
7 |
|a CIRCUITOS LOGICOS
|9 157766
|
| 650 |
|
7 |
|a CODIFICACION
|9 161576
|
| 650 |
|
7 |
|a LENGUAJES DE PROGRAMACION
|9 144013
|
| 650 |
|
7 |
|a OPERADORES LOGICOS
|9 191087
|
| 650 |
|
7 |
|a SECUENCIA LOGICA
|9 213164
|
| 650 |
|
7 |
|a CONTROL DE SISTEMAS
|9 197810
|
| 100 |
1 |
|
|a Chu, Pong P.
|9 209433
|
| 300 |
|
|
|a xxiii, 669 p. :
|b il. ; diagrs. ;
|c 26 cm.
|
| 504 |
|
|
|
| 942 |
|
|
|2 udc
|c LIB
|
| 999 |
|
|
|c 154111
|d 154111
|