|
|
|
|
| LEADER |
00851nam a22002535a 4500 |
| 001 |
2409 |
| 003 |
AR-SjUIP |
| 005 |
20200305104542.0 |
| 008 |
920616t1984 ||| 00 0 eng d |
| 040 |
|
|
|a AR-SjUIP
|c AR-SjUIP
|
| 900 |
|
|
|a Proyecto Huarpe
|b 6699
|c 6699
|d Proyecto Huarpe
|
| 020 |
|
|
|a 098381649
|
| 245 |
0 |
0 |
|a LOGIC, minimization algorithms for VLSI synthesis /
|c by Robert K. Brayton ... [et al.].
|
| 260 |
|
|
|a Boston :
|b Kluwer Academic,
|c 1984.
|
| 500 |
|
|
|a Bibliografía: p. 174-192.
|
| 080 |
|
|
|a 681.31
|2 3 abrev. esp.
|
| 650 |
|
7 |
|
| 700 |
1 |
|
|a Brayton, Robert K.
|9 198852
|
| 490 |
1 |
|
|a The Luwer International series in Engineering and Computer Science.
|
| 830 |
|
0 |
|a The Luwer International series in Engineering and Computer Science.
|9 198853
|
| 300 |
|
|
|a 193 p. ;
|c 23 cm.
|
| 504 |
|
|
|
| 942 |
|
|
|2 udc
|c LIB
|
| 999 |
|
|
|c 145142
|d 145142
|