Datos convertidos
{
"id": "I19-R120-10915-22643",
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"I19-R120-10915-226432019-08-23T14:27:53Z http:\/\/sedici.unlp.edu.ar\/handle\/10915\/22643 Metrics for fast, low-cost adders in FPGA Simonelli, Daniel Horacio V\u00e1zquez, Mart\u00edn Osvaldo 2003-10 2003-10 2012-10-19T12:01:06Z en Ciencias Inform\u00e1ticas sistema operativo Metrics for Fast Metrics Architectures Low-Cost Adders FPGA In this paper several adder design techniques that probed to be very effective in full-custom integrated circuit design are presented as well as the conclusions regarding its implementation on FPGA. Particularly, in this work, Xilinx XC4000E family is selected as target technology and results achieved without using dedicated carry logic present in these devices are evaluated. This paper aims to substantiate the fact that these techniques indeed reduce delay time in other technologies than full custom design and from these results decide if it is worth trying implementations using XC4000E dedicated carry logic. Eje: Arquitectura, Redes y Sistemas Operativos (ARSO) Red de Universidades con Carreras en Inform\u00e1tica (RedUNCI) Objeto de conferencia Objeto de conferencia http:\/\/creativecommons.org\/licenses\/by-nc-sa\/2.5\/ar\/ Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5) application\/pdf 1384-1392"
],
"institution": [
"Universidad Nacional de La Plata"
],
"institution_str": "I-19",
"repository_str": "R-120",
"collection": [
"SEDICI (UNLP)"
],
"language": [
"Ingl\u00e9s"
],
"topic": [
"Ciencias Inform\u00e1ticas",
"sistema operativo",
"Metrics for Fast",
"Metrics",
"Architectures",
"Low-Cost Adders",
"FPGA"
],
"spellingShingle": [
"Ciencias Inform\u00e1ticas",
"sistema operativo",
"Metrics for Fast",
"Metrics",
"Architectures",
"Low-Cost Adders",
"FPGA",
"Simonelli, Daniel Horacio",
"V\u00e1zquez, Mart\u00edn Osvaldo",
"Metrics for fast, low-cost adders in FPGA"
],
"topic_facet": [
"Ciencias Inform\u00e1ticas",
"sistema operativo",
"Metrics for Fast",
"Metrics",
"Architectures",
"Low-Cost Adders",
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],
"description": "In this paper several adder design techniques that probed to be very effective in full-custom integrated circuit design are presented as well as the conclusions regarding its implementation on FPGA. Particularly, in this work, Xilinx XC4000E family is selected as target technology and results achieved without using dedicated carry logic present in these devices are evaluated. This paper aims to substantiate the fact that these techniques indeed reduce delay time in other technologies than full custom design and from these results decide if it is worth trying implementations using XC4000E dedicated carry logic.",
"format": [
"Objeto de conferencia",
"Objeto de conferencia"
],
"author": [
"Simonelli, Daniel Horacio",
"V\u00e1zquez, Mart\u00edn Osvaldo"
],
"author_facet": [
"Simonelli, Daniel Horacio",
"V\u00e1zquez, Mart\u00edn Osvaldo"
],
"author_sort": "Simonelli, Daniel Horacio",
"title": "Metrics for fast, low-cost adders in FPGA",
"title_short": "Metrics for fast, low-cost adders in FPGA",
"title_full": "Metrics for fast, low-cost adders in FPGA",
"title_fullStr": "Metrics for fast, low-cost adders in FPGA",
"title_full_unstemmed": "Metrics for fast, low-cost adders in FPGA",
"title_sort": "metrics for fast, low-cost adders in fpga",
"publishDate": [
"2003"
],
"url": [
"http:\/\/sedici.unlp.edu.ar\/handle\/10915\/22643"
],
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"AT vazquezmartinosvaldo metricsforfastlowcostaddersinfpga"
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}