Análisis e implementación de operaciones aritméticas en base diez sobre dispositivos de lógica programable
General purpose microprocessors available on today's market does not provide hardware support for performing mathematical operations based on decimal representation. Instead, those chips implement arithmetic units using binary representation which provide a better performance. This fact is d...
Guardado en:
| Autor principal: | |
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| Formato: | Artículo revista |
| Lenguaje: | Español |
| Publicado: |
Universidad Nacional del Centro de la Provincia de Buenos Aires, Facultad de Ciencias Exactas
2018
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| Materias: | |
| Acceso en línea: | https://www.ridaa.unicen.edu.ar/handle/123456789/1946 |
| Aporte de: |
| Sumario: | General purpose microprocessors available on today's market does not provide
hardware support for performing mathematical operations based on decimal
representation. Instead, those chips implement arithmetic units using binary
representation which provide a better performance. This fact is due to the two-state
nature of electronic transistors. However, many commercial and scientific applications
strictly requires computed calculations to be exactly the same as human performed.
Actually, those systems that does not provide decimal floating point support, must
adapt theirs operands to be computed assuming a difference with the real result. Errors
inherited by precision loss may violate legal conditions, cause millionaire losses and
even human life risk. The first alternative to smooth this is to give a special treatment to
floating point operations at software level. This solution avoids result errors but
increases computing resources and deteriorates calculation speed. A second popular
alternative requires operands and result conversion from/to radix-10 and using the
traditional computation. However, successive conversions could fall into precision loss.
The decimal floating point arithmetic boosts the IEEE 754-1985 floating point standard
adding decimal representation support and leading to IEEE 754-2008. The new standard
states storage formats and treatment algorithms for handling decimal floating point
numbers.There is a special interest on using FPGA programmable devices as hardware
accelerators performing decimal floating point operations that meet IEEE 754-2008.
This work proposes the analysis, design and implementation of different
algorithms to solve arithmetic operations based on radix-10 and targeted to Xilinx
programmable devices. The addessed operations are: addition, subtraction, square root
and decimal logarithm. The fundamental aim of this work is to promote the design and
implementation of both soft and firm cores of arithmetic units that meet IEEE 754-
2008 standard. A secondary intent is to establish synthesis strategies to be used on
Xilinx tools for implementing electronic devices that supports radix-10 arithmetic operations. |
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