A low cost advance encryption standard (AES) co-processor implementation

The need for privacy has become a major priority for both governments and civilians desiring protection from signal interception. Widespread use of personal communications devices has only increased demand for a level of security on previously insecure communications. This paper presents a novel low...

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Detalles Bibliográficos
Autores principales: Hernandez, Orlando J., Sodon, Thomas, Adel, Michael, Kupp, Nathan
Formato: Articulo
Lenguaje:Inglés
Publicado: 2008
Materias:
Ciencias Informáticas
Cryptographic controls
FPGA Design
VLSI Design
Acceso en línea:http://sedici.unlp.edu.ar/handle/10915/9617
http://journal.info.unlp.edu.ar/wp-content/uploads/JCST-Apr08-2.pdf
Aporte de:
SEDICI (UNLP) de Universidad Nacional de La Plata
id I19-R120-10915-9617
record_format dspace
institution Universidad Nacional de La Plata
institution_str I-19
repository_str R-120
collection SEDICI (UNLP)
language Inglés
topic Ciencias Informáticas
Cryptographic controls
FPGA Design
VLSI Design
spellingShingle Ciencias Informáticas
Cryptographic controls
FPGA Design
VLSI Design
Hernandez, Orlando J.
Sodon, Thomas
Adel, Michael
Kupp, Nathan
A low cost advance encryption standard (AES) co-processor implementation
topic_facet Ciencias Informáticas
Cryptographic controls
FPGA Design
VLSI Design
description The need for privacy has become a major priority for both governments and civilians desiring protection from signal interception. Widespread use of personal communications devices has only increased demand for a level of security on previously insecure communications. This paper presents a novel low-cost architecture for the Advanced Encryption Standard (AES) algorithm utilizing a field programmable gate array (FPGA). In as much as possible, this architecture uses a bit-serial approach, and it is also suitable for VLSI implementations. In this implementation, the primary objective was not to increase throughput or decrease latency, but to balance these factors in order to lower the cost. A focus on low cost resulted in a design well-suited for SoC implementations. This allows for scaling of the architecture towards vulnerable portable and cost-sensitive communications devices in consumer and military applications.
format Articulo
Articulo
author Hernandez, Orlando J.
Sodon, Thomas
Adel, Michael
Kupp, Nathan
author_facet Hernandez, Orlando J.
Sodon, Thomas
Adel, Michael
Kupp, Nathan
author_sort Hernandez, Orlando J.
title A low cost advance encryption standard (AES) co-processor implementation
title_short A low cost advance encryption standard (AES) co-processor implementation
title_full A low cost advance encryption standard (AES) co-processor implementation
title_fullStr A low cost advance encryption standard (AES) co-processor implementation
title_full_unstemmed A low cost advance encryption standard (AES) co-processor implementation
title_sort low cost advance encryption standard (aes) co-processor implementation
publishDate 2008
url http://sedici.unlp.edu.ar/handle/10915/9617
http://journal.info.unlp.edu.ar/wp-content/uploads/JCST-Apr08-2.pdf
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