Utilizing block size variability to enhance instruction fetch rate

In the past, instruction fetch speeds have been improved by using cache schemes that capture the actual program flow. In this paper, we elaborate on the architecture and operation of an instruction cache named Variable-Sized Block Cache (VSBC) that also makes use of the dynamic behavior of a program...

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Guardado en:
Detalles Bibliográficos
Autores principales: Beg, Azam, Chu, Yul
Formato: Articulo
Lenguaje:Inglés
Publicado: 2007
Materias:
Ciencias Informáticas
Cache memories
Variable-Sized Block Cache (VSBC)
Acceso en línea:http://sedici.unlp.edu.ar/handle/10915/9548
http://journal.info.unlp.edu.ar/wp-content/uploads/JCST-Apr07-5.pdf
Aporte de:
SEDICI (UNLP) de Universidad Nacional de La Plata

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