Metrics for FIR Filters based on distributed arithmetic in FPGA

In this paper, metrics regarding different architectures for distributed arithmetic based FIR filters in FPGA are presented. Main filter parameters are described as well as diverse design techniques applied: pipelining, bit-serial, digit-serial y bit-parallel. Each filter description was written in...

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Detalles Bibliográficos
Autores principales: Vázquez, Martín Osvaldo, Simonelli, Daniel Horacio, Acosta, Nelson
Formato: Objeto de conferencia
Lenguaje:Inglés
Publicado: 2004
Materias:
Ciencias Informáticas
Parallel processing
Distributed
Metrics
distributed arithmetic
FPGA
FIR
Acceso en línea:http://sedici.unlp.edu.ar/handle/10915/22495
Aporte de:
SEDICI (UNLP) de Universidad Nacional de La Plata
Descripción
Sumario:In this paper, metrics regarding different architectures for distributed arithmetic based FIR filters in FPGA are presented. Main filter parameters are described as well as diverse design techniques applied: pipelining, bit-serial, digit-serial y bit-parallel. Each filter description was written in VHDL at RTL level. For achieving this goal no relative location (rloc) technique was used what redounds on more generic and expensive designs than those available through Core Generator tool. Implementation has been carried out over FPGAs belonging to Xilinx Virtex II family.

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