Reducing the LSQ and L1 data cache power consumption

In most modern processor designs, the HW dedicated to store data and instructions (memory hierarchy) has become a major consumer of power. In order to reduce this power consumption, we propose in this paper two techniques, one to filter accesses to the LSQ (Load-Store Queue) based on both timing and...

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Detalles Bibliográficos
Autores principales:	Apolloni, Rubén, Carazo, P., Castro, Fernando, Chaver, Daniel, Piñuel, Luis, Tirado Fernández, Francisco
Formato:	Objeto de conferencia
Lenguaje:	Español
Publicado:	2010
Materias:	Ciencias Informáticas sistema operativo data System architectures LSQ filter accesses
Acceso en línea:	http://sedici.unlp.edu.ar/handle/10915/19346
Aporte de:	SEDICI (UNLP) de Universidad Nacional de La Plata

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