Cita APA (7a ed.)

Sanchez, R. M., Reyes, B. T., Pola, A. L., & Hueda, M. R. (2024). An FPGA-based emulation platform for evaluation of time-interleaved ADC calibration systems.

Cita Chicago Style (17a ed.)

Sanchez, Raúl M., Benjamín T. Reyes, Ariel L. Pola, y Mario R. Hueda. An FPGA-based Emulation Platform for Evaluation of Time-interleaved ADC Calibration Systems. 2024.

Cita MLA (8a ed.)

Sanchez, Raúl M., et al. An FPGA-based Emulation Platform for Evaluation of Time-interleaved ADC Calibration Systems. 2024.