Source-Synchronous Networks-On-Chip Circuit and Architectural Interconnect Modeling /
This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how...
Guardado en:
| Autor principal: | |
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| Otros Autores: | , |
| Formato: | Libro electrónico |
| Lenguaje: | Inglés |
| Publicado: |
New York, NY :
Springer New York : Imprint: Springer,
2014.
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| Materias: | |
| Acceso en línea: | http://dx.doi.org/10.1007/978-1-4614-9405-8 |
| Aporte de: | Registro referencial: Solicitar el recurso aquí |
Tabla de Contenidos:
- Introduction
- Clock Distribution for fast Networks-on-Chip
- Fast Network-on-Chip Design
- Fast On-Chip Data transfer using Sinusoid Signals
- Conclusion and Future Work.